Online ISSN
1751-861X
Print ISSN
1751-8601
IET Computers & Digital Techniques
Volume 1, Issue 3, May 2007
Volumes & issues:
Volume 1, Issue 3
May 2007
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- Author(s): C. Landrault and E.J. Marinissen
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, page: 145 –145
- DOI: 10.1049/iet-cdt:20079007
- Type: Article
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Editorial: Selected best papers from ETS’06
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- Author(s): V. Kerzérho ; P. Cauvet ; S. Bernard ; F. Azaïs ; M. Comte ; M. Renovell
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 146 –153
- DOI: 10.1049/iet-cdt:20060136
- Type: Article
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The trend towards highly-integrated electronic devices has lead to a growth of system-in-package and system-on-chip technologies, where data converters play a major role in the interface between the real analogue world and digital processing. Testing these converters with accuracy and at low cost represents a big challenge because the observability and controllability of these blocks is reduced and the test operation requires a lot of time and expensive analogue instruments. A new design-for-test technique called ‘analogue network of converters’ is presented. This technique aims at testing a set of analogue-to-digital converters and digital-to-analogue converters in a fully digital setup (using a low-cost digital tester). The proposed method relies on a novel processing of the harmonic distortion generated by the converters and requires an extremely simple additional circuitry and interconnects. - Author(s): B. Laquai ; M. Braun ; S. Walther ; G. Schulze
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 154 –158
- DOI: 10.1049/iet-cdt:20060133
- Type: Article
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The increasing bandwidth requirements of mainstream computing and consumer products, as well as the inefficiency of embedded clock interfaces in terms of latency, protocol overhead and power requirements, have caused the traditional source synchronous interfaces such as dynamic random access memory to break the Gigabit range. Above 1 Gbps dynamic effects such as drift and jitter might become critical for traditional test approaches. At the same time, the usage of dedicated source synchronous ATE HW solutions is challenged by the economic pressure and the flexibility requirements. A new test methodology based on traditional ATE architecture which can deliver both, detailed characterisation results or just a pass/fail decision for a parametric validation in production – depending on the actual test requirement – is described here. - Author(s): B. Kim ; H. Shin ; J.-H. Chun ; J.A. Abraham
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 159 –169
- DOI: 10.1049/iet-cdt:20060154
- Type: Article
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Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships between signatures and specification. In addition, it is difficult to precisely control physical factors in built-in self-test circuitry, which can cause errors in the signatures. A methodology for efficient prediction of circuit specifications with optimised signatures has been proposed. The proposed optimised signature-based alternate test methodology accurately predicts the specifications of a Device Under Test (DUT) using a strong correlation mapping function. Hardware measurement results show that this approach can be effectively used to predict the specifications of a DUT, with a significant reduction in the prediction error compared with previous approaches. - Author(s): D. Han ; S. Bhattacharya ; A. Chatterjee
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 170 –179
- DOI: 10.1049/iet-cdt:20060145
- Type: Article
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Because of aggressive technology scaling and multi-GHz operating frequencies of radio frequency (RF) devices, parametric failure test and diagnosis of RF circuitry is becoming increasingly important for the reduction of production test cost and faster yield ramp-up. A low-cost test and diagnosis method is proposed for multi-parametric faults in wireless systems that allows for the accurate prediction of the end-to-end specifications as well as the specifications of all the embedded RF modules. The procedure is based on application of an optimised test stimulus and extraction of its transient test response envelopes at RF signal nodes using a simple diode-based envelope detector. The test response is down-converted to lower frequencies compared to the operating frequency, thus eliminating the need to make RF measurements using expensive instrumentation. The specifications as well as the diagnostic information are computed from the test response of the envelope detector using statistical models. It is shown that the resulting information (features) in the transient envelope can accurately predict a host of test specifications using a single test configuration and test response capture event. Hardware measurement data from a 1.575 GHz transceiver shows that the test specifications of the system as well as the modules can be predicted with a high degree of accuracy using this method.
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC
Flexible and scalable methodology for testing high-speed source synchronous interfaces on automated test equipment (ATE) with multiple fixed phase capture and compare
Predicting mixed-signal dynamic performance using optimised signature-based alternate test
Low-cost parametric test and diagnosis of RF systems using multi-tone response envelope detection
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- Author(s): V. Gherman ; H.-J. Wunderlich ; J. Schloeffel ; M. Garbers
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 180 –186
- DOI: 10.1049/iet-cdt:20060131
- Type: Article
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Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault testing is not trivial as this necessitates the application of pattern pairs. As a consequence, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. With this in mind, the authors consider the so-called transition fault model, which is widely used for complexity reasons, and an extension of a DLBIST scheme for transition fault testing is presented. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated using difficult-to-test industrial designs.
Deterministic logic BIST for transition fault testing
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- Author(s): G. Di Guglielmo ; F. Fummi ; C. Marconcini ; G. Pravadelli
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 187 –196
- DOI: 10.1049/iet-cdt:20060139
- Type: Article
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A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state space by exploiting an easy-to-traverse extended finite state machine (FSM) model has been described. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the extended FSM. Testing of hard-to-detect faults is thus improved. The generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows also to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.
Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM
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- Author(s): A.M. Amory ; K. Goossens ; E.J. Marinissen ; M. Lubaszewski ; F. Moraes
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 197 –206
- DOI: 10.1049/iet-cdt:20060152
- Type: Article
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A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip (NOC) to transport test data to embedded cores, and hence eliminates the need for a conventional dedicated test access mechanism (TAM), such as a TestRail or test bus. The approach leaves both the tester, as well as the embedded core and its test unchanged, while the functional interconnect can handle the test data transport as a regular data application. The functional interconnect is required to offer guaranteed throughput and zero latency variation, a service that is available in many buses and networks. For 672 example cases based on the ITC'02 System-on-Chip (SOC) Test Benchmarks, the new approach in comparison with the conventional approach shows an average wrapper area increase of 14.5%, which is negligible at the SOC level, especially since the dedicated TAM can be eliminated. Futhermore, the new approach decreases the core test length by 3.8% on average. - Author(s): F. Poehl ; M. Beck ; R. Arnold ; J. Rzeha ; T. Rabenalt ; M. Goessel
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 207 –212
- DOI: 10.1049/iet-cdt:20060129
- Type: Article
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p.
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Technology and product ramp-up suffers increasingly from systematic production defects. Diagnosis of scan-test fail data plays an important role in yield enhancement, as diagnosis of scan fail data helps to understand and overcome systematic production defects. Acquisition of scan fail data during high-volume production may lead to significant test time overhead. A new on-chip architecture is presented that evaluates scan-test results and stores relevant scan diagnostic information on chip. Scan diagnostic data is unloaded for offline analysis after the scan test has been finished. Unloading scan diagnostic data from chip requires only very little test time overhead. Moreover, the proposed technique is automatic test equipment independent and accelerates test program development. A detailed implementation example, based on a state-of-the-art SoC device, is given.
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism
On-chip evaluation, compensation and storage of scan diagnosis data
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- Author(s): G. Xu and A.D. Singh
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 213 –219
- DOI: 10.1049/iet-cdt:20060142
- Type: Article
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p.
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Most scan-based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but requiring a fast scan enable. A low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge is presented. The new design is much more efficient when compared with other recent proposals and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve transition delay fault coverage approaching 95% for the ISCAS89 benchmarks. - Author(s): Z. Zhang ; S.M. Reddy ; I. Pomeranz ; J. Rajski ; B.M. Al-Hashimi
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 220 –229
- DOI: 10.1049/iet-cdt:20060135
- Type: Article
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Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low-power DFT techniques and test generation procedures have been proposed. Segmented scan has been shown to be an effective technique in addressing test power issues in industrial designs . To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. For the first time, it has been demonstrated that segmented scan facilitates increased delay fault coverage without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 and ITC-99 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 7.4% while simultaneously reducing the peak switching activity caused by capture cycles by over 20.4%. - Author(s): S.K. Goel ; M. Meijer ; J. Pineda de Gyvez
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 230 –236
- DOI: 10.1049/iet-cdt:20060147
- Type: Article
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The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is one of the main hurdles in low-power applications. Power switches enable power gating functionality, that is one or more parts of the SOC can be powered-off during standby mode thus leading to savings in the SOC's overall power consumption. To this end, a circuit and a method to test power switch is presented. The proposed method allows for the testing of on/off functionality. In case of segmented power switches, individual failing segments can be identified by using the proposed test strategy. The method only requires a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead.
Scan cell design for launch-on-shift delay tests with slow scan enable
Enhancing delay fault coverage through low-power segmented scan
Efficient testing and diagnosis of faulty power switches in SOCs
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- Author(s): A. Bosio ; S. Di Carlo ; G. Di Natale ; P. Prinetto
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 237 –245
- DOI: 10.1049/iet-cdt:20060137
- Type: Article
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Memory testing commonly faces two issues: the characterisation of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them. Among the different types of algorithms proposed for testing static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured. The continuous evolution of the memory technology requires the constant introduction of new classes of faults, such as dynamic and linked faults. Presented here is March AB, a march test targeting realistic memory static linked faults and dynamic unlinked faults. Comparison results show that the proposed march test provides the same fault coverage of already published algorithms reducing the test complexity and therefore the test time.
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs
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- Author(s): Y.-J. Huang and J.-F. Li
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 246 –255
- DOI: 10.1049/iet-cdt:20060134
- Type: Article
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With shrinking transistor sizes and growing transistor density, testing neighbourhood pattern-sensitive faults (NPSFs) is increasingly important for semiconductor memories. A test methodology for detecting active NPSFs (ANPSFs) and static NPSFs (SNPSFs) in ternary content addressable memories (TCAMs) is presented. March-like and two-group test methods are two commonly used testing techniques for NPSFs in random access memories. Because of the special TCAM cell structure, however, using a unique test algorithm with only either a March-like or a two-group test operations are not time-efficient. A test methodology that employs both March-based and two-group testing to cover 100% ANPSFs and SNPSFs in TCAMs is proposed. The total test complexity of the proposed test methodology is 156 N for an N×K-bit TCAM. No TCAM circuit modification is needed to support the proposed test methodology. - Author(s): Q. Xu ; B. Wang ; A. Ivanov ; F.Y. Young
- Source: IET Computers & Digital Techniques, Volume 1, Issue 3, p. 256 –264
- DOI: 10.1049/iet-cdt:20060128
- Type: Article
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The test scheduling problem for built-in self-tested embedded SRAMs (e-SRAMs) when data retention faults (DRFs) are considered is addressed here. We proposed a ‘retention-aware’ test power model by taking advantage of the fact that there is near-zero test power during the pause time for testing DRFs. The proposed test scheduling algorithm then utilises this new test power model to minimise the total testing time of e-SRAMs while not violating given power constraints, by scheduling some e-SRAM tests during the pause time of DRF tests. Without losing generality, we consider both cases where the pause time for DRFs is fixed and cases where it can be varied. Experimental results show that the proposed ‘retention-aware’ test power model and the corresponding test scheduling algorithm can reduce the testing time of e-SRAMs significantly with negligible computational time.
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults
Test scheduling for built-in self-tested embedded SRAMs with data retention faults
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