Key parameters of analog‐to‐digital converters (ADCs) are their sampling rate and dynamic range. Power consumption and cost of an ADC are directly proportional to the sampling rate; hence, it is desirable to keep it as low as possible. The dynamic range of an ADC also plays an important role, and ideally, it should be greater than the signal's; otherwise, the signal will be clipped. To avoid clipping, modulo folding can be used before sampling, followed by an unfolding algorithm to recover the true signal. Here, the authors present a modulo hardware prototype that can be used before sampling to avoid clipping. The authors’ modulo hardware operates prior to the sampling mechanism and can fold higher frequency signals compared to existing hardware. The authors present a detailed design of the hardware and also address key issues that arise during implementation. In terms of applications, the authors show the reconstruction of finite‐rate‐of‐innovation signals, which are beyond the dynamic range of the ADC. The authors’ system operates at six times below the Nyquist rate of the signal and can accommodate eight times larger signals than the ADC's dynamic range.

The authors present a hardware prototype of a high‐dynamic range analog‐to‐digital converter (ADC) where a folding operation enhances the dynamic range. The authors show sampling and perfect reconstruction of different classes of signals whose dynamic ranges are larger than that of ADC's dynamic range.image

A compact frequency reconfigurable beam switching antenna based on a single‐layer frequency selective face (FSS) is proposed in this paper. The proposed antenna consists of a dual‐band dipole antenna and a single‐layer FSS with hexagonally arrangement. The omnidirectional radiation pattern of the dipole antenna designed as a radiation source and surrounded by the FSS can be converted into directional radiation pattern sweeping along the entire azimuthal plane at two single frequency of 2.4 or 5 GHz. The frequency selection is achieved by controlling the diode state of the FSS unit, and the beam switching is realised by a specific combination of electromagnetic wave reflection or transmission from the hexagonal FSS. The novelty lies in applying the hexagonal arrangement to a dual single‐frequency single‐layer FSS unit. This will not destroy the reflection or transmission characteristics of the FSS unit, but also contribute to reduce the antenna size and achieve a low cost. To validate the design, a prototype is fabricated and measured. The single‐layer FSS antenna with a volume of 57 mm × 57 mm × 58.5 mm can be scanned in 12 steps along the azimuth plane at 2.4 and 5 GHz, respectively.

The omnidirectional radiation pattern of the dipole antenna designed as a radiation source and surrounded by the FSS can be converted into directional radiation pattern sweeping along the entire azimuthal plane at two single frequency of 2.4 or 5 GHz.The novelty lies in applying the hexagonal arrangement to a dual single‐frequency single‐layer FSS unit.image

The authors’ present a silicon‐on‐insulator (SOI) laterally diffused metal‐oxide‐semiconductor field‐effect transistor (LDMOSFET) with β‐Ga₂O₃ , which is a large bandgap semiconductor (β‐LDMOSFET), for increasing breakdown voltage (V_BR) and power figure of merit. The fundamental purpose is to use a β‐Ga₂O₃ semiconductor instead of silicon material due to its large breakdown field. The characteristics of β‐LDMOSFET are analysed to those of standard LDMOSFET, such as V_BR, ON‐resistance (R_ON), power figure of merit (PFOM), and radio frequency (RF) performances. The effects of RF, such as gate‐drain capacitance (C_GD), gate‐source capacitance (C_GS), transit frequency (f _T ), and maximum frequency of oscillation (f _MAX) have been investigated. The β‐LDMOSFET structure outperforms performance in the V_BR by increasing it to 500 versus 84.4 V in standard LDMOSFET design. The suggested β‐LDMOSFET has R_ON ~ 2.3 mΩ.cm⁻² and increased the PFOM (V_BR ²/R_ON) to 108.6 MW/cm². All the simulations are done with TCAD and simulation models are calibrated with the experimental data.

The authors’ present a LDMOSFET with β‐Ga2O3 for increasing breakdown voltage and power figure of merit. The β‐LDMOSFET structure outperforms performance in the V_BR, increasing it to 500 versus 84.4 V in a standard LDMOSFET design. The suggested β‐LDMOSFET has R_ON ∼ 2.3 m & ohm; cm⁻² and increased the PFOM (V_BR ²/R_ON) to 108.6 MW/cm².image

Significant progress has been made in manufacturing emerging technologies in recent years. This progress implemented in‐memory‐computing and neural networks, one of today's hottest research topics. Over time, the need to process complex tasks has increased. This need causes the emergence of intelligent processors. A nonvolatile associative memory based on spintronic synapses utilising magnetic tunnel junction (MTJ) and carbon nanotube field‐effect transistors (CNTFET)‐based neurons is proposed. The proposed design uses the MTJ device because of its fascinating features, such as reliable reconfiguration and nonvolatility. At the same time, CNTFET has overcome conventional complementary metal‐oxide‐semiconductor shortcomings like the short channel effect, drain‐induced barrier lowering, and poor hole mobility. The proposed design is simulated in the presence of process variations. The proposed design aims to increase the number of weights generated in the synapse for higher memory capacity and accuracy. The effect of different tunnel magnetoresistance (TMR) values (100%, 200%, and 300%) on the performance and accuracy of the proposed design has also been investigated. This investigation shows that the proposed design performs well even with a low TMR value, which is very important and remarkable from the fabrication point of view.

A nonvolatile associative memory based on spintronic synapses utilizing magnetic tunnel junction (MTJ) and carbon nanotube field‐effect transistors (CNTFET)‐based neurons is proposed. The proposed design uses the MTJ device because of its fascinating features, such as reliable reconfiguration and nonvolatility. At the same time, CNTFET has overcome conventional CMOS shortcomings like the short channel effect, drain‐induced barrier lowering, and poor hole mobility.image

This paper presents simulation and measurement results of a 2–4 GHz octave bandwidth interference suppression circuit. The circuit accomplishes the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The delay is adjusted by varying the drain voltage of cold‐FET connected high electron mobility transistors acting as varactors. Two types of periodically‐loaded delay lines are compared: a uniform and a tapered design. A simple theoretical study, relating the delays and amplitudes in the interferometer circuit branches, is developed to inform the design. Two interference suppression hybrid circuits are implemented, and measurements demonstrate a 25–40 dB notch across the 2.24–4 GHz range for the uniform delay line, and 2.32–4.13 GHz for the tapered design. The return loss for both designs remains below 10 dB. Measurements with two tones spaced 0.5 and 1 GHz for varying tone power are performed to quantify suppression. The circuit can handle an input power of 37 dBm and maintains performance with two simultaneous 25 dBm tones spaced 0.5 GHz apart. Linearity is characterised with 10 MHz two‐tone measurements, and the circuit demonstrates a 3rd‐order intercept input power larger than 30 dBm for control biases above −12 V.

Two 2–4 GHz octave bandwidth interference suppression circuits accomplishe the function of a tunable frequency notch through an interferometer architecture. The relative delay in the interferometer paths is varied with GaN monolithic microwave integrated circuit tunable delay lines. The designs have good notch performance demonstrating a 25–40 dB notch across the 2.5–4 GHz range, while maintaining a good return below 10 dB.image