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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 9, Issue 5, September 2015


Volume 9, Issue 5

September 2015

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    • High-speed energy-efficient bi-directional transceiver for on-chip global interconnects
      Decoder architecture for generalised concatenated codes
      Subquadratic space complexity Gaussian normal basis multipliers over GF(2 m ) based on Dickson–Karatsuba decomposition
      Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic
      Holistic design strategy for high-selectivity low-loss integrated millimetre-wave image-reject filters
      Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design
      Time-to-digital convertor based on resolution control
      High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter

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