This paper presents the design and testing results of a complementary metal–oxide–semiconductor double-bulk harmonic-rejection (HR) mixer for wideband applications. An optimal gate-source bias voltage in the sub-threshold regime of the input transistor is found theoretically to achieve maxim HR by analysing the mixing mechanism of double-bulk mixer; and a double-bulk mixer has been designed and fabricated to verify the theoretical analysis. Test results substantiate the existence of the optimal bias point for HR of double-bulk-driven mixer when the sinusoidal local oscillator (LO) is applied. This simple but effective topology can achieve higher than 36, 44, 60 and 62 dB HR ratio for the third-, fifth-, seventh- and ninth-order of LOs, respectively, over broadband. The double-bulk mixer which input bandwidth is from 250 MHz to 3 GHz, including the buffer, consumes 5 mA current from 1 V power supply; the mixer core only consumes 1.5 mA current.

The most important dual relationships of the duality principle include the relationship between node and mesh, and the relationship between branch and branch. They both appear in the patterns of duality, and the latter is also further represented as dual relations of the passive elements, of the active elements, of the controlled-source elements, of the switching elements and also of the two-port coupling elements. This study presents the branch-dualising rule of the duality principle by joining the topological graphs of dual circuits together with physical properties of their elements, proves its adaptability for all the regular circuits and gives a solution for non-regular circuit elements with each just put into a dual element list of the rule one after another after finding its specific dualising mode. The branch-dualising rule is easy and practical for use to obtain the dual circuit diagram directly from its primal, greatly expanding the range of applications of the duality principle.

In this paper, a new configuration of operational amplifier -based square-wave oscillator is proposed. The circuit performs an impedance-to-period (Z–T) conversion that, instead of a voltage integration typically performed by other solutions presented in the literature, is based on a voltage differentiation. This solution is suitable as first analogue uncalibrated front-end for capacitive and resistive (e.g. relative humidity and gas) sensors, working also, in the case of capacitive devices, for wide variation ranges (up to six capacitive variation decades). Moreover, through the setting of passive components, its sensitivity can be easily regulated. Experimental measurements, conducted on a prototype printed circuit board, with sample passive components and using the commercial capacitive humidity sensor Honeywell HCH-1000, have shown good linearity and accuracy in the estimation of capacitances, having a baseline or reaching a value ranging in a wide interval [picofarads–microfarads], as well as, with a lower accuracy, in the evaluation of more reduced variations of resistances, ranging from kiloohms to megaohms, also when compared with other solutions presented in the literature.

The architecture, design and implementation of a low power complementary metal-oxide semiconductor (CMOS) class-G audio amplifier with gradual power-supply switching (GPSS) are presented. The proposed class-G amplifier output stage strategically uses the parallel connection of a class-AB output stage operating from smaller supplies (V _DDL/V _SSL), and a class-C output stage (with crossover from V _SSL to V _DDL) operating from higher supplies (V _DDH/V _SSH). GPSS is achieved using an efficient biasing scheme with level shifters. Moreover, the proposed biasing scheme in conjunction with negative feedback enables low distortion during the power-supply transition. Experimentally, the class-G amplifier prototype achieves a −82.5 dB THD + N, a peak load power of 50 mW and a quiescent power consumption of 350 μW. The proposed class-G amplifier was implemented in a standard CMOS 90 nm technology and occupies an active silicon area of 0.08 mm².

Quantum-dot cellular automata, as the successor of metal–oxide semiconductor field-effect transistors, are one of the promising nanotechnology devices, which have attracted myriad researchers in the recent decade. In this technology, coplanar wire crossing is one of the unique specifications that can reduce its reliability. In the present study, a heuristic method is introduced using the Karnaugh-Map (K-Map) to minimise the number of wire crossing as the first step. Afterwards, it attempts to replace each wire crossing with three non-wire crossing XOR gates that reduce all wire crossings to zero as the second step. Experimental results reveal that, reducing wire crossings to zero, the authors method for 3-variable functions lowers the number of gates about 54, 42, 58 and 59%, respectively, in comparison with K-Map, Genetic, Gate-Optimise and Universal Quantum-dot Cellular Automata Logic Gate (UQCALG) methods. For 4-variable functions, their method decreases the number of gates almost 64 and 58%, respectively.

Although miniaturised fuel cells store more energy than lithium-ion batteries and super capacitors, they source less power, which means they cannot power as many functions. Their power-dense counterparts, however, cannot sustain life for long, which is why mixing technologies is appealing. Still, microsystems are tiny and react quickly, so their supply circuits must also be small and fast. For this reason, the dual-source hysteretic single-inductor 0.18 µm complementary metal–oxide–semiconductor charger-supply system presented and discussed here draws constant power from an energy-dense source and supplementary power from a rechargeable power-dense battery. The prototyped system supplies and responds to 1–4 mA load dumps within one or two clock cycles with 73% peak efficiency and recharges the battery with excess power from the energy-dense source. When managed to draw supplementary power from a battery this way and loaded with a microsystem that idles at 10 μW and peaks to 4 mW, as in the case of typical wireless sensors, the combined weight of the sources required is 68% less than those of the state-of-the-art.

This paper highlights achievement of broadband high performance power amplifier (PA) line up for mobile two-way radio applications. In typical two-way radio applications the input radio-frequency signal to the first PA stage comes directly from the voltage controlled oscillator, with typically 3 dBm power. Owing to high output power requirement (∼80 W) of mobile radio applications, up to three PA device stages are normally cascaded (pre-driver, driver and final PA stage). The key point in the design of the PA line up concerns the final stage. Here, this paper introduces a design methodology based on parallel-combined impedance matching technique (from theoretical derivation) enables the designers to develop broadband PA with actual PA device impedance (implementation of new generation laterally diffused metal–oxide–semiconductor device). Experimental results demonstrated output power of ∼80 W and gain of 45 dB, while preserving efficiency of 55% over the bandwidth from 760 to 870 MHz. According to author's knowledge, this amplifier demonstrated highest efficiency with 13 V DC supply (operating at 80 W) in UHF broadband frequency with high gain operation (more than 45 dB) up to date.

Realisations of filters in signal processing using interconnects as delay elements have been presented. Normally, these filters are implemented using switched capacitor technique. However, in digital realisations of these filters, flip flops are used for obtaining the delays. Here, the implementation of these filters using interconnects has been presented. Moreover, filter architectures which acts as basic building blocks for other complex filter structures have been explored and discussed. Spice simulations of these basic building blocks are carried out using BSIM 4.3 50 nm technology with a supply voltage of 1 V.

In this paper a new solution for a highly linear, high speed open loop (OL) residue amplifier for applications in high-speed pipelined analogue-digital converters is proposed. The proposed amplifier has a voltage gain of 4 (V/V) with <0.2% non-linearity error and 1.2 V_p-p output swing. The amplifier is compensated for process variations by using a novel gain control mechanism, thus maintains the linearity in all process conditions and also in the presence of a mismatch. The proposed amplifier is designed in 0.35 μm complementary metal-oxide semiconductor process, and the settling time is approximately 2 ns when driving two 1 pF single ended capacitive loads. It consumes 38 mW power from a 2.8 V supply and occupies 0.073 mm² of die area. Simulations are performed in HSPICE using level 49 models.

The authors propose an asynchronous-logic (async) quasi-delay-insensitive (QDI) autonomous signal-validity half-buffer (ASVHB) realisation approach for low power sub-threshold operation (V _DD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used exclusively to simplify the circuit implementation for QDI protocol. Second, the ASVHB realisation approach applies the fine-grained gate-level method, which propagates data through a single-cell datapath pipeline to maximise the throughput rate. Third, the ASVHB realisation approach adopts the static-logic implementation, which maintain stable output states (by connecting them directly to the power rails), to feature high robustness for sub-threshold operation. They compare their ASVHB realisation approach against the competitive reported weak-conditioned half-buffer (WCHB) and pre-charged half-buffer (PCHB) realisation approaches. The WCHB and PCHB library cells, on average, require ∼2.1 × and ∼1.9 × more transistors than the ASVHB library cells. With respect to a 3-stage pipeline realisation, the WCHB and PCHB pipelines, on average, require 1.8 × and 1.5× more transitions per-cycle than the ASVHB pipeline. They design an async 32-bit arithmetic and logic unit (ALU) based on the proposed ASVHB realisation approach (at 65 nm CMOS process). Their ASVHB ALU occupies 0.092 mm², and in many merits, outperforms the WCHB and PCHB counterparts. The WCHB and PCHB counterparts require ∼1.7 × and ∼1.4× more transistors, respectively, than their design. At the sub-threshold voltage of V _DD = 0.2 V, the WCHB and PCHB counterparts dissipate ∼1.7× and ∼2.6× more energy, respectively, and are, respectively, ∼0.95× and ∼0.73× slower throughput.