This paper proposes a numerical method for accurate time-domain noise simulation of mixed analogue/digital electrical circuits that in principle do not admit a periodic steady-state working condition, such as fractional ΔΣ phase-locked loops (PLLs). By means of a tool known as saltation matrix, which allows dealing with non-smooth vector fields, a variational approach is adopted. The power spectral density of a noisy electrical variable is computed by applying the Thomson's multitaper method (MTM) to the numerical solution of the stochastic variational model of the circuit. This allows to resort to a single transient simulation run, thus avoiding cpu time consuming Monte-Carlo-like approaches. The effectiveness of the proposed method is shown by comparing simulation results related to a commercial fractional ΔΣ PLL with experimental data.

The authors report on Coulomb blockade effect in the PtSi/porous Si Schottky barrier. A model of two-dimensional multi-tunnelling junction (2D-MTJ) can explain the blockade characteristic of this barrier. Using the SIMON simulator, the electrical characteristics of the proposed model were investigated. The results show that simulated current–voltage curves achieve a reasonable fit with the measured data and the present model can be used to study the PtSi/porous Si Schottky barrier behaviour. In accordance with both the studies, Coulomb blockade phenomenon is observed in current oscillation and single-electron effect of this device at low temperatures (5 K) is justified using the 2D-MTJ model. In addition, it indicates that by increasing the current value with temperature and for high drain voltages, PtSi/porous Si Schottky barrier behaves like a single island single-electron tunnelling (SET) junction as previously reported by Raissi et al.

The number of applicable challenge–response pairs (CRPs) in physical unclonable functions (PUFs) is critical especially for authentication protocols in security systems. Ideally, full read-out of all CRPs should be infeasible and CRPs should be independent from each other for a highly secure system. CRP concept is not defined in ordering-based ring oscillator (RO) PUFs presented in the literature. In this paper, the authors propose two methods for enhanced CRP set in ordering-based RO-PUFs and analyse their performance in terms of uniqueness and area efficiency. Next, they propose three secure usage scenarios based on enhanced CRP set methods, preventing the CRPs from leaking information about each other. With the proposed systems, 100% robust, area and power efficient and secure PUF structures with exponential number of CRPs become possible that are very convenient especially for authentication protocols.

This paper presents a battery-less non-contact temperature measurement system powered by energy harvesting from intentional human action. The conversion between the human action and electrical energy is provided by a hand-crank electromagnetic (EM) converter. The AC voltage generated by the EM converter has time-varying amplitude and frequency and is rectified by a metal–oxide-semiconductor field-effect transistor-based voltage doubler active rectifier circuit. The harvested energy is efficiently stored into multiple capacitors by the innovative sequential charging of storage capacitors technique, and used to power a micro electro mechanical system thermopile sensor with related signal conditioning electronics plus a liquid-crystal display to visualise the temperature readings. With a force of about 29.4 N over 2 cm applied to the EM converter, the power management circuit is able to extract an energy of 27.5 mJ and power the non-contact temperature measurement system for about 33 s.

A CMOS variable gain amplifier (VGA) based on a novel linear and tunable triode transconductor is presented. The proposed transconductor employs local negative feedback for linearisation controlling the drain voltage of the input transistors biased in the triode region. The new design is able to operate at low supply voltage and the stability is guaranteed. The transconductor features a 47.75 dB dc gain and a 4.23 MHz unity gain frequency with a power consumption of only 91 µA. To show the feasibility of the proposed transconductor, a VGA has been fabricated. Measurement results for a 0.13 µm CMOS design show a −3 dB bandwidth above 2.8 MHz and a third-order harmonic distortion at 500 kHz below −46 dB over the whole gain range. The VGA exhibits a maximum power consumption of only 395 µW from a single 1.2 V supply.

This paper presents the observation of intermediate state in the quantum dot gate field-effect transistors (QDGFETs) in silicon-on-insulator (SOI) substrate. Silicon dioxide (SiO₂)-cladded silicon (Si) quantum dots (QDs) are site-specifically self-assembled on the top of SiO₂ tunnel gate insulator on SOI substrates. Charge carrier tunnelling from the inversion channel to the QD layers on top of the gate insulator is responsible for the generation of intermediate state. Charge tunnelling is also verified by the C–V characteristics of the MOS device having same insulator structure as the gate region of the QDGFET. Considering the transfer of charge carriers from the inversion channel to two layers of SiO₂-cladded Si QDs, a model based on self-consistent solution of Schrödinger and Poisson equations, is also presented, to explain the generation of intermediate state.

This study presents a Volterra series approach to analyse injection-locked non-harmonic oscillators. We show that by depicting the voltage transfer characteristics of comparators using hyperbolic tangent functions, non-harmonic oscillators can be analysed analytically using a set of Volterra circuits that are linear, have the same topology and element values but different inputs. We further show that the larger lock range of non-harmonic oscillators as compared with that of their harmonic counterparts is because of the harsher non-linear characteristics of these oscillators and the lower-order attenuation of the high-order frequency components of the oscillators. The reduced non-linear characteristics of ring oscillators because of the absence of positive feedback also gives rise to a smaller lock range as compared with relaxation oscillators. These theoretical findings are validated using both the simulation results of relaxation oscillators and ring oscillators designed in IBM 130 nm complementary metal oxide semiconductor technology and the measurement results of ring oscillators implemented using commercial ICs.

This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition-based spur reducing technique including the repetition mismatch.