The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit ΔΣ frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.

A Class E power amplifier offers high efficiency approaching 100% for an ideal case. A new wide bandwidth Class E power amplifier design has been introduced combining a parallel-circuit load network with reactance compensation technique and high-order harmonic suppression circuit. The proposed topology has been discussed based on theory and its experimental verification. A hardware prototype was designed and built, and measurement results showed drain efficiency of 70% and second harmonic rejection of more than 84 dBc (as well as higher harmonics), and output power level more than 6.5 W with ±0.5 dB power flatness, across very high frequency (VHF) band (136–174 MHz). The performance achieved demonstrated highest harmonic suppression across wide bandwidth for VHF range according to authors’ knowledge. Simulations of power performance (i.e. efficiency and output power) were verified by measurements, and good agreements were obtained.

This study presents a novel short-circuit protection technique for DC–DC buck converters. The required short-circuit operating frequency is derived in order to avoid the effect of inherent propagation delay in the controller and power transistors. In this design, the short-circuit switching frequency is approximately 31% of the normal value. Simultaneously, the peak current limit is decreased to about 40% of the normal value to lower the power dissipation when a short-circuit event occurs. Once the fault condition is removed, the converters can automatically return to normal operation smoothly by clamping the soft-start signal using the feedback voltage of the output. A buck converter with the proposed technique has been successfully simulated and verified by a 0.6-μm CDMOS technology. The simulation results show that the power loss is only 17.1% of the constant current limit during the prolonged short-circuit situation, which significantly enhances the reliability of the chip. Furthermore, the converter is able to achieve smooth self-recovery as soon as the fault status is released.

Reducing the leakage power in embedded static random access memory (SRAM) memories is critical for low-power applications. Raising the source voltage of SRAM cells through diode transistor in standby mode reduces the leakage currents effectively. However, in order to preserve the state of the cell in standby mode, the source voltage cannot be raised beyond a certain level. To achieve that, the size of the required diode transistor becomes larger, as the supply voltage shrinks in the nano-complementary metal oxide semiconductor (CMOS) technologies. In this work, an area efficient power gating technique with capability of post-silicon trimming of the voltage across SRAM cell is presented. Proposed scheme provides many options to trim the SRAM source voltage (ranging from 50 to 150 mV in steps of 25 mV approximately.) with 3% area overhead when applied to complete SRAM bank. The scheme has been illustrated with a 16 kb SRAM macro at 28 nm CMOS technology at 0.85 V supply voltage. Sector-based power gating is presented which enables leakage savings while memory is in the active mode. The area overhead of the presented scheme is 8% when applied to SRAM bank array split into sectors.

The design and physical implementation of an embedded memory utilising bit-area efficient hybrid gain cell is presented. The memory cells in this work are composed of a high-threshold NMOS write transistor and a standard-threshold NMOS read transistor. The bit data are stored on the parasitic capacitances within the cells. Owing to the combination of low subthreshold-leakage write device and high mobility read device, this NMOS-based hybrid 2T gain cell exhibits much improved data retention and read performance in a compact bit area. The memory arrays operate with a logic-compatible supply voltage; SRAM-like I/O interface; chip-select-controlled 128-row refresh; and non-destructive read with speed comparable with 6T SRAM, but 65% smaller cell area. Measurement results from a 32 kbit pseudo-SRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed embedded memory techniques.

This study provides a comprehensive review of decision feedback equalisation (DFE) for multi-giga-bit-per-second (Gbps) data links. The state-of-the-art of DFE for multi-Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross-talk and their impact on data transmission are investigated. The fundamentals of both near-end and far-end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi-Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.

This research study analyses the impact of semi-conductor (t _osc) and dielectric (t _ox) thicknesses on top contact (TC) and bottom contact (BC) organic thin film transistors (OTFTs) using Atlas 2-D numerical device simulation. Thickness of each layer is varied from 20 to 150 nm. The parameters such as electric field, charge carrier distribution and trap density are analysed from device physics point of view with variations in organic semi-conductor layer and dielectric thicknesses. A decrease of 22% in TC to BC current ratio is observed for maximum increase in t _osc, whereas, it remains almost constant at unity with variations in t _ox. Furthermore, the maximum mobility for TC is achieved at t _osc of 20 nm and reduces monotonically with further increase in thickness because of lowering of average charge. However, its highest value is obtained at 60 nm for BC structure that declines with positive or negative change in t _osc. Besides this, the threshold voltage (V _t) shows a reduction of 50% for both the structures on scaling down t _ox from 150 to 20 nm. Furthermore, the ON to OFF current ratio is found to be more dependent on t _osc as compared with t _ox. This is because of a dominant impact of t _osc reduction on OFF current as compared with impact of t _ox reduction on the ON current. Additionally, a decrease in contact resistance (R _C) is observed in TC structure for thicker active layer while operating at lower V_gs . However, at high gate voltage, t _osc maps to the access resistance that results in higher R _C values.

This study presents a versatile precision rectifier. The circuit yields a positive half-wave signal, a negative half-wave signal, a positive full-wave signal and a negative full-wave signal into one single structure. The personal computer simulation program with integrated circuit emphasis (PSPICE) simulation is performed to examine the performance of the new circuit. The experimental result is also confirmed workability of the proposed circuit.