Periodic steady-state behaviour of cross-coupled LC-tank oscillator is of critical importance in ultra-low power, low-voltage transceiver circuits. Understanding the major factors affecting amplitude, oscillation frequency and power consumption would lead to more optimised oscillator design particularly for short-range wireless transceivers. This study presents a new approach for evaluating the amplitude of the main component, oscillation frequency and power consumption of cross-coupled LC-tank oscillator. Three major factors, affecting oscillator functionality are examined. In order to obtain a general design methodology, the effects of oscillator parameters such as transistors’ sizes, inductor and capacitor values are investigated. An intuitive discussion about oscillator behaviour and a design procedure are presented. The theoretical results are verified by circuit simulations in the 0.18 µm CMOS process.

This study presents a parallel very large scale integrated circuits architecture for an intra-predictor based on a fast 4 × 4 algorithm. For real-time scheduling, the proposed algorithm overcomes the data dependency between intra-prediction and intra-coding, thereby improving coding performance and reducing the number of coding cycles. The high-speed architecture for intra-prediction includes configurable computation cores to process YUV components using 10 pixel parallelism. Prediction for one macro-block (MB) coding (luminance: 4 × 4 and 16 × 16 block modes; chrominance: 8 × 8 block modes) can all be completed within 256 cycles. The proposed architecture achieves throughput of 410 kMB/s, suitable for 1920 × 1080/35 Hz 4:2:0 HDTV encoder at a working frequency of 105 MHz.

In this study, the failure rate of flip-flops in future 16 nm complementary metal-oxide-semiconductor (CMOS) technologies is investigated. Using transistor level Monte Carlo simulations, the authors studied the influence of process variations and long term aging on the yield. The statistical distribution of the switching time (clock-to-Q delay) is shown to be highly asymmetric compared to a Gaussian distribution leading to a drastically enhanced fraction of very slow or metastable samples. Moreover, the failure rates will rise additionally during the device lifetime because of aging effects. To improve the yield the authors investigated several possible countermeasures including enhanced supply voltage or ensuring larger data-to-clock times as well as process and circuit optimisation.

A transistor level implementation of an improved matrix multiplier for high-speed digital signal processing applications based on matrix element transformation and multiplication is reported in this study. The improvement in speed was achieved by rearranging the matrix element into a two-dimensional array of processing elements interconnected as a mesh. The edges of each row and column were interconnected in torus structure, facilitating simultaneous implementation of several multiplications. The functionality of the circuitry was verified and the performance parameters for example, propagation delay and dynamic switching power consumptions were calculated using spice spectre using 90 nm CMOS technology. The proposed methodology ensures substantial reduction in propagation delay compared with the conventional algorithm, systolic array and pseudo number theoretic transformation (PNTT)-based implementation, which are the most commonly used techniques, for matrix multiplication. The propagation delay of the implemented 4 × 4 matrix multiplier was only ∼2 µs, whereas the power consumption of the implemented 4 × 4 matrix multiplier was ∼3.12 mW only. Improvement in speed compared with earlier reported matrix multipliers, for example, conventional algorithm, systolic array and PNTT-based implementation was found to be ∼67, ∼56 and ∼65%, respectively.

In this study, the authors cover French very high frequency (VHF) band with a novel all-digital fast lock delayed looked loop (DLL)-based frequency synthesiser. Since this new architecture uses a digital signal processing unit instead of phase-frequency detector, charge pump and loop filter in conventional DLL therefore it shows better jitter performance, locktime and convergence speed. To obtain in-phase input and output signals in DLLs, optimisation methods are used in the proposed architecture. The proposed architecture is designed to cover channels of French VHF band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells and f _REF = 16 MHz which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.5 μs which is equal to 8 clock cycles of reference clock. All of simulation results show superiority of the proposed structure.

Even though enumeration is a common technique adapted in very large-scale integration (VLSI) floorplanning, its impact in terms of wirelength, whitespace, as well as runtime on the floorplanning has never been investigated comprehensively. In this study, enumerative floorplanner (EFP) is proposed here by using enumeration. The impact of the maximum enumeration order on VLSI floorplan layout is investigated and the tradeoff relationship with the wirelength, area and runtime is analysed as well. In EFP, dynamic programming enumerative clustering (DEC) technique is employed to reduce the worst-case time complexity and runtime. DEC also introduces the same number of possible permutations of modules while reducing the redundancy created in enumerative clustering (EC) without the usage of dynamic programming. A straightforward cost function is adapted to assist DEC to select the best cluster permutation, and a rigorous local refinement is proposed to compensate the EC's impact on the floorplan wirelength. Experimental results show that EFP is a high performance floorplanner when compared to existing methods in terms of robustness, scalability and stability.

This study presents a digital phase detector-based approach for estimating and synchronising phase variations between clock domains. Instead of waiting for the resolution of metastability (with finite probability of failure), the authors propose a metastability avoidance algorithm, based on a sampling method for asynchronous signals. The results, using 90 nm inovation for high performance microelectronics (IHP) technology, show that the proposed design is about 1.5 times faster and provides a 35% improvement in Energy-Delay Product compared with the state-of-the-art approaches. Moreover, it completely prevents metastability failures.

An interface for reading the output of nanomagnetic logic (NML) is indispensable in order for NML to interact with existing CMOS ICs. Two alternative designs readout interface circuit (RIC1 and RIC2) for NML RIC are proposed based on dual barriers magnetic tunnel junction (DBs-MTJ), which is composed of two fixed layers (with anti-parallel magnetisation state) and a common free layer. RIC1 utilises the same layer order of DB-MTJ to form an up–down structure, whereas RIC2 exploits the reversed layer order of DB-MTJ to form a left–right structure. They utilise the three-terminal approach to realise the self-reference readout scheme. The magnetisation state of the free layers in RIC1 and RIC2 are controlled by the fringing field from NML and biased by the designed on-chip clock field. The sensing circuits in RIC1 and RIC2 utilise dynamic current mode and pre-charge sense amplifier, respectively. The simulation results indicate that RIC1 and RIC2 can achieve comparable magnetoresistance values, and also realise the logical readout scheme by itself. The switching time in RIC1 is less than that in RIC2, whereas time delay for data transportation in RIC1 is more than that in RIC2. RIC2 is more amenable than RIC1 to the current fabrication process technology.