Three-dimensional integrated circuits (3D-ICs) bring about new challenges to chip thermal management because of their high heat densities. Micro-channel-based liquid cooling and thermal through-silicon-vias (TSVs) have been adopted to alleviate the thermal issues in 3D-ICs. Thermal TSV enables higher interlayer thermal conductivity thereby achieving a more uniform thermal profile. Although somewhat effective in reducing temperatures, they are limited by the nature of the heat sink. On the other hand, micro-channel-based liquid cooling is significantly capable of addressing 3D-IC cooling needs, but consumes a lot of extra power for pumping coolant through channels. This study proposes a hybrid 3D-IC cooling scheme which combines micro-channel liquid cooling and thermal TSV with one acting as heat removal agent, whereas the other enabling beneficial heat conduction paths to the micro-channel structures. The experimental results show that the proposed hybrid cooling scheme provides much better cooling capability than using only thermal TSVs, although consuming 56% less cooling power compared with pure micro-channel cooling.

This study presents theoretical analysis and synthesis algorithm for multithreshold threshold gates (MTTGs) built of resonant tunnelling diodes (RTDs). The aim of the synthesis is to find a structure of an MTTG gate and relations between all the RTDs given an arbitrary Boolean function of n variables. The contribution of this study is 3-fold: first the authors formulate a functional model of the MTTG gate in which output is given as the difference of two min functions each taking weighed sums of input signals as arguments. Second, it is shown that any Boolean function can be represented as a min/max composition of hyperplanes (weighed sum of input signals) representing threshold functions. Later a procedure is proposed that transforms min/max composition to a difference of two min functions that corresponds to the MTTG structure. Finally, the authors show that the complexity of the resulting the MTTG gate depends on the number of thresholds k in the threshold decomposition of Boolean function and propose a dedicated threshold decomposition procedure that minimises the resulting number of thresholds. As a result, synthesised MTTG circuit is composed of at most (k + 1)(n + 1) RTD devices and (k + 1)n switching elements.

Multi-processor system on chip (MPSoC) consists of multiple cores communicating via an on-chip communication backplane. An application to be executed on an MPSoC is represented using a task graph where a node represents an operation to be scheduled on a core and the edges represent the communication between these operations. Typically task graph scheduling on MPSoC is done statically during hardware–software co-design, based on estimated execution times. Static scheduling makes a program non-portable, hence dynamic scheduling is preferred. In this study, the authors present hardware-based dynamic feedback-driven task rescheduling heuristic that executes in real time. This task scheduling heuristic is based on the observation that during the course of execution, an application goes through a phase where a sub-graph (phase graph) of the application task graph repeatedly executes for a very large number of times. The proposed approach is iterative, where the schedule length of a phase graph converges to a smaller value in subsequent iterations. Experimental results show (i) real-time scheduling can be performed using proposed game theoretic approach which converges to a minimum in fewer than 100 iterations (ii) reducing the schedule length ranging 3–16% as compared with greedy heuristic.

Continuous and aggressive scaling of semiconductor technology has led to persistent and dominant nanoscale effects on analogue/mixed-signal (AMS) circuits. Design space exploration and optimisation costs using conventional techniques have increased to infeasible levels. Hence, growing research for alternative design and metamodelling techniques with a much reduced design space exploration and optimisation cost and high level of accuracy, continues to be very active. This study presents a geostatistical inspired metamodelling and optimisation technique for fast and accurate design optimisation of nano-complementary metal oxide semiconductor (CMOS) circuits. The design methodology proposed integrates a simple Kriging technique with efficient and accurate prediction characteristics as the metamodel generation technique. A gravitational search algorithm (GSA) is applied on the generated metamodel (substituted for the circuit netlist) to solve the design optimisation problem. The proposed methodology is applicable to AMS circuits and systems. Its effectiveness is illustrated with the optimisation of a 45 nm CMOS thermal sensor. With six design parameters, the design optimisation time for the thermal sensor is decreased by 90% and produces an improvement of 36.8% in power consumption. To the best of the authors' knowledge this is the first work to use GSA for analogue design optimisation.

To date, ternary quantum-dot cellular automata (QCA) has been especially investigated and also is being advanced. Nonetheless, it should be possible to make interactions between binary QCA and ternary QCA circuits in order to have a versatile platform of designing. On the other hand, one of the most important concerns in QCA is minimising wire crossings because of low robustness caused by their manufacturing process and operational defects. In this study, a novel ternary-to-binary (and vice versa) converter is introduced firstly and a novel coplanar wire crossing scheme is proposed and presented afterwards. The latter scheme uses both kinds of binary and ternary QCA cells and provides a reliable crossover. Detailed circuit designs and results are presented to show correct functionality of the proposed circuits.

Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.

Security in embedded systems is of critical importance since most of our secure transactions are currently made via credit cards or mobile phones. Power analysis-based side channel attacks have been proved as the most successful attacks on embedded systems to retrieve secret keys, allowing impersonation and theft. State-of-the-art solutions for such attacks on public key cryptographic algorithms, such as elliptic curve cryptography, mostly in software, hinder performance and repeatedly attacked using improved techniques. To protect these public key ciphers from both simple power analysis and differential power analysis, as a hardware solution, we propose to take advantage of the inherent parallelisation capability in multi-modulo residue number systems (RNS) architectures to obfuscate the secure information. Random selection of moduli is proposed to randomly choose the moduli sets for each key bit operation. This solution allows us to prevent power analysis, although still providing all the benefits of RNS. In this study, the authors show that differential power analysis, cross correlation analysis and correlation power analysis for a simple binary double-and-add operation are thwarted using their solution.

Energy efficiency is considered to be the most critical design parameter for ubiquitous and mobile computing systems. With consumers expecting improved functionality and performance from these systems without compromising on battery life, there is urgent need to explore emerging technologies that can overcome the limitations of CMOS and deliver greater energy efficiency. The potential of one such prospective metal oxide semiconductor field effect transistor replacement device, the tunnel FET (TFET), is evaluated in this study. Novel circuit designs are presented to overcome unique design challenges posed by TFETs. Further, the impact of TFETs at different levels of design abstraction is characterised by evaluating a novel sparse prefix tree adder and a field programmable gate array. A considerable improvement in delay and significant reduction in energy is observed because of the combined impact of circuit and technology co-exploration.