Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 6, Issue 2, March 2012
Volumes & issues:
Volume 6, Issue 2
March 2012
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- Author(s): J. Lota ; M. Al-Janabi ; I. Kale
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 71 –78
- DOI: 10.1049/iet-cds.2011.0194
- Type: Article
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The present approaches on predicting stability of delta–sigma (Δ–Σ) modulators are mostly confined to DC inputs. This poses limitations as practical applications of Δ–Σ modulators involve a wide range of signals other than DC such as multiple-sinusoidal inputs for speech modelling. In this study, a quasi-linear model for Δ–Σ modulators with non-linear feedback control analysis is presented that accurately predicts stability of single-loop one-bit higher-order Δ–Σ modulators for multiple sinusoids. Theoretical values are shown to match closely with the simulation results. The results of this study would significantly speed up the design and evaluation of higher-order single-loop Δ–Σ modulators with increased dynamic ranges for various applications that require multiple-sinusoidal inputs or any general input composed of a finite number of sinusoidal components. - Author(s): M. Azarmehr ; R. Rashidzadeh ; M. Ahmadi
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 79 –84
- DOI: 10.1049/iet-cds.2011.0279
- Type: Article
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p.
79
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Passive radio frequency identification tags extract energy from incoming electromagnetic waves to power up their internal circuitry. Such a limited source of power demands efficient circuits to minimise the power consumption. In this work a new technique is proposed to design a low-power ring oscillator in which the voltage swing of internal nodes are constrained to lower the dynamic power consumption. The proposed power reduction technique can be employed for RFID tags operating over different frequency bands from low frequency (LF) to microwave. A low-power oscillator operating in the medium-frequency range (6–16 MHz) for applications such as electronic article surveillance and item management has been implemented in this work. Post-layout simulation results using STMicroelectronics CMOS 65 nm technology indicate that the proposed method can reduce the power consumption by more than 25%. - Author(s): J. Lee
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 85 –94
- DOI: 10.1049/iet-cds.2011.0054
- Type: Article
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85
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As the number of IP cores that can be integrated into a single chip has increased significantly in recent years, various types of multi-layered bus architectures are now being used. However, a reckless use of bus layers may lead to an excessive number of wires and low-resource utilisation. To reduce such waste, researches have studied automated on-chip bus design methods for optimal architecture synthesis. This study expands the existing studies in two aspects. First, it considers all possible topologies and redefines the existing exploration problem, whereas the existing studies assume only a few types of topologies. Second, the study includes an exploration process based on a new on-chip bus protocol, system-on-chip network protocol (SNP), as well as processes based on existing protocols to solve the redefined problem. After the time complexity is investigated, it is found that the problem is NP-hard. Accordingly, this study proposes fast search algorithms that can be applied to each of the exploration steps. The proposed algorithms are implemented as a software program of exploration. The overall reduction ratio of the time complexity reaches about three millionths, with a maximal 16% increase in communication time (CT). Considering todays design life cycle, this seems to be a good trade-off. - Author(s): R.-L. Chen ; H.-W. Ting ; S.-J. Chang
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 95 –102
- DOI: 10.1049/iet-cds.2011.0192
- Type: Article
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This study presents a 6-bit 2.7 GS/s low-power digital-to-analogue converter (DAC) for ultra-wideband transceivers. A ‘2(thermometer)+4(binary)’ segmented architecture is chosen to reach a compromise between the current source cell's area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DAC's dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in the analogue and digital parts, respectively. Moreover, the compact de-glitch latch presented in this study simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13 µm 1P8M complementary metal-oxide semiconductor technology with the active area of 0.0585 mm2. The measured differential non-linearity and integral non-linearity are less than 0.09 and 0.11 least significant bit, respectively. The measured spurious-free dynamic range is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW with a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step than other published arts. - Author(s): S. Maheshwari and B. Chaturvedi
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 103 –110
- DOI: 10.1049/iet-cds.2011.0213
- Type: Article
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This study presents four new voltage mode first-order all-pass filters using a newly developed single Dual-X current conveyor with buffered output. The proposed circuits possess high-input impedance, low-output impedance and require either two or three passive elements. An application of new circuits is also given in realising the quadrature oscillator. Non-ideal and sensitivity analysis is also performed. The circuit performances are depicted through PSPICE simulations, which show good agreement to theoretical anticipations. Possible realisation using AD-844 along with some experimental results are also given for completeness sake. The new circuits are expected to enhance the already-existing knowledge on the subject.
Accurate stability prediction of one-bit higher-order delta–sigma modulators for multiple-sinusoidal inputs
Low-power oscillator for passive radio frequency identification transponders
Design methodology for on-chip bus architectures using system-on-chip network protocol
Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers
High-input low-output impedance all-pass filters using one active element
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- Author(s): J.A. Jiménez Tejada
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 111 –112
- DOI: 10.1049/iet-cds.2012.0047
- Type: Article
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111
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- Author(s): J. Brochet ; B. Aventurier ; F. Templier
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 113 –117
- DOI: 10.1049/iet-cds.2010.0367
- Type: Article
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The authors fabricated bottom-gate (BG) back-channel etched (BCE) thin-film transistors with hydrogenated polymorphous silicon (pm-Si:H) as the channel material. This material is obtained using the same low-cost plasma-enhanced chemical vapour deposition (PECVD) techniques as amorphous silicon. The authors first show the improvement of the threshold voltage stability of pm-Si:H TFTs under bias stress compared to a-Si:H counterparts. Then, pm-Si:H TFTs degradation is investigated under different gate bias stress conditions. It has been found that the degradation mechanisms are dependent on the gate stress conditions involving state creation in the channel material and charge trapping at the channel/gate SiNx interface. - Author(s): J.W. Jin ; M. Oudwan ; D. Daineka ; O. Moustapha ; Y. Bonnassieux
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 118 –121
- DOI: 10.1049/iet-cds.2011.0124
- Type: Article
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The universal simulation program with integrated circuit emphasis (SPICE) model for hydrogenated amorphous silicon thin-film transistor is largely used in circuit simulation. This model has more than 10 parameters to be extracted through experimental data, and the optimal method to determine them is still open to discussion. In this study, the authors propose a new method for the extraction of the main above-threshold regime parameters. This method can be used regardless of the resistance value between the channel and the source–drain. The parameters extracted with this method are less sensitive on experimental data selection than the ones obtained through conventional methods. In addition, these parameters successfully describe the experimental data. - Author(s): M. Raja and W. Eccleston
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 122 –129
- DOI: 10.1049/iet-cds.2011.0199
- Type: Article
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Analytical device models for disordered organic Schottky diodes and thin-film transistors are presented. The models are developed taking into consideration the strong dependency of the charge mobility on carrier concentration. The drain current expressions are consequently developed in terms of the essential device parameters and applied voltages, to a power exponent of the characteristic temperature associated with the disordered nature of the semiconductor. Upon validation, better agreement of the experimental data is achieved with the disordered model rather than the conventional crystalline equation. Interestingly, under certain conditions, the disordered model reverts back to the conventional model, suggesting the latter to be a special case. Finally, to facilitate the circuit development, alternative design parameters to the mobility term are proposed. - Author(s): A. Castro-Carranza ; M. Estrada ; J.C. Nolasco ; A. Cerdeira ; L.F. Marsal ; B. Iñíguez ; J. Pallarès
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 130 –135
- DOI: 10.1049/iet-cds.2010.0372
- Type: Article
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The authors present an analytical and continuous model for the total charges at the gate, drain and source electrodes for organic thin-film transistors (OTFTs), from which analytical expressions of the total capacitances are obtained. Under the quasi-static approximation, the model parameters are extracted using the previously developed unified model and parameter extraction method (UMEM). The capacitance model is valid above threshold voltage. It guarantees continuity of the expressions for the capacitance at the transition between linear and saturation regimes, as well as takes into account the overlap capacitance. Comparisons between modelled and experimental CGG values are shown. - Author(s): R. Picos ; E. Garcia-Moreno ; M. Roca ; B. Iniguez ; M. Estrada ; A. Cerdeira
- Source: IET Circuits, Devices & Systems, Volume 6, Issue 2, p. 136 –140
- DOI: 10.1049/iet-cds.2011.0169
- Type: Article
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Most of the applications of circuits that are currently in existence use mainly digital circuits. However, interfacing with the external world is a task that can be only accomplished by analog circuits. Thus, to obtain a functional system, some attention must be paid to them, especially when using organic thin-film transistors. In this case, some new issues arise that are very different from those in the digital world. Analog circuits pose a special problem to analog designers. Owing to their low mobilities, they present very low gains, and biasing them in the right point becomes a critical point. Another critical aspect is the high parameter dispersion, which makes analog designs quite complex. In this study, we will try to present a similar strategy, adapted to the specific case of organic TFTs.
Editorial: Thin-film-transistor modelling for circuit simulation
Stability of hydrogenated polymorphous silicon thin-film transistors under DC electrical stress
Parameter extraction method for universal amorphous silicon thin-film transistors simulation program with integrated circuit emphasis model
Analytical device models for disordered organic Schottky diodes and thin-film transistors for circuit simulations
Organic thin-film transistor bias-dependent capacitance compact model in accumulation regime
Optimised design of an organic thin-film transistor amplifier using the gm/ID methodology
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