Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 5, Issue 4, July 2011
Volumes & issues:
Volume 5, Issue 4
July 2011
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- Author(s): S. Jahanbakht and F. Farzaneh
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 257 –266
- DOI: 10.1049/iet-cds.2010.0209
- Type: Article
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p.
257
–266
(10)
Floquet eigenfunctions and Floquet exponents are encountered in stability and noise analysis of circuits operating at large signal periodic regime. It is analytically verified that the spectrum vectors of the left-hand and right-hand Floquet eigenfunctions and the Floquet exponents (Floquet eigenpairs) are members of the harmonic balance eigenvalues and eigenvectors (HB eigenpairs). The relationships between other HB eigenpairs with the Floquet eigenpairs are discussed. This discussion leads to a practical algorithm for computing the Floquet eigenpairs through HB eigenpairs. Furthermore, it is analytically verified that the main arguments of the study are consistent with the orthogonality/biorthogonality relations between different Floquet eigenfunctions. The new approach has been applied to a P-HEMT oscillator at 10.2 GHz and very good agreement between the Floquet eigenpairs computed through the new approach and the ones computed through the time-domain integration is observed. - Author(s): B.H. Stark ; G.D. Szarka ; E.D. Rooke
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 267 –274
- DOI: 10.1049/iet-cds.2010.0199
- Type: Article
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p.
267
–274
(8)
Remote sensors powered by energy harvesting need to restart successfully after long periods of no available energy, during which all stored energy may have been depleted. This start-up is affected by known phenomena such as ‘lock-up’ and ‘voltage collapse’. In this study, the authors address these phenomena in the context of energy harvesting where the energy required for a sense and transmit cycle is accumulated over long time periods at low power. A voltage-detecting switch with very low power consumption is proposed, which avoids system lock-up. This start-up circuit uses an array of discrete MOSFETs operated in their sub-threshold regions. A performance metric for start-up circuits is proposed. ‘Minimum operating power’ is the harvester power level below which the load does not start up. Reducing this minimum operating power thus reduces the required size of harvester or increases the application range. For the proposed circuit, a minimum operating power of 3.5 µW is derived experimentally, and recommendations are provided to further reduce this. The minimum operating power of the proposed circuit is shown to be a strong function of capacitive surge current, and surge current associated with undefined logic states. The transient contribution of components to the quiescent power is analysed through experiment. Simulation shows that increased temperature not only reduces the minimum operating power, but also reduces the energy available to the load. - Author(s): M.K. Kazimierczuk and D. Murthy-Bellur
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 275 –284
- DOI: 10.1049/iet-cds.2010.0163
- Type: Article
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p.
275
–284
(10)
This study presents the derivations of the voltage transfer functions of the amplifier A, the feedback network β, the loop gain T, the closed-loop gain Af and also the characteristic equation for the common-gate (CG) Colpitts oscillator, using the small-signal model of the metal-oxide-semiconductor field-effect transistor (MOSFET) CG Colpitts oscillator. Using the characteristic equation, the expressions for the oscillation frequency of the sinusoidal output voltage and the condition for oscillation in steady state are derived. The characteristic equation is also used to obtain a plot of trajectories of the closed-loop poles of the CG Colpitts oscillator by varying the MOSFET small-signal transconductance gm. The locations of the complex conjugate poles of closed-loop gain that depict the starting and steady-state conditions for oscillations are presented. Nyquist plots of the loop gain are given to illustrate the startup and steady-state conditions of oscillations. Simulation and experimental results to verify the theory are also given. - Author(s): M.H. Moaiyeri ; A. Doostaregan ; K. Navi
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 285 –296
- DOI: 10.1049/iet-cds.2010.0340
- Type: Article
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p.
285
–296
(12)
Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple-Vt design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40% less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature. - Author(s): L. Zou and T. Larsen
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 297 –302
- DOI: 10.1049/iet-cds.2010.0330
- Type: Article
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p.
297
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(6)
For many biomedical implantable systems, power is transferred into implants through an inductively coupled coil pair. When the receiver coil enters a strong magnetic field generated by the transmitter coil, the implanted device can receive more than needed power. This may lead to the generation of so high received voltages that the implant may be damaged (which may also have consequences for the patient). In addition, during the regulation of the rectified DC voltage, the low-dropout (LDO) voltage regulator exhibits poor power efficiency if the input voltage is much higher than the output voltage. Thus, the corresponding heating effect is increased. This study introduces a high-voltage CMOS dynamic power control circuit that can be integrated in the implantable power receiver front-end. The circuit is capable of auto-detuning the receiver inductive-capacitive (LC) tank to adjust the power reception level according to the actual magnetic field strength. The experimental results show that the power control circuit reduces the impact of the varied magnetic field on the rectified voltage. Also, the prototype measurements show that the power efficiency of the LDO regulator increases from 35 to 72%, when the power control circuit activates the detuning function. - Author(s): W.-S. Yu and T.-S. Wu
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 303 –320
- DOI: 10.1049/iet-cds.2010.0292
- Type: Article
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303
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(18)
The authors present an H∞ tracking performance design scheme via fuzzy adaptive observer-based control for chaotic Chua's systems with output time delay. The Takagi–Sugeno-type fuzzy linear model with adaptation capability is used to approximate the chaotic system. Based on the fuzzy model, a two-layer fuzzy observer is used to reconstruct the system states according to output time delay. A state feedback controller is developed to override the non-linearities, time delays and external disturbances, while the linguistic information is utilised by setting the membership functions of fuzzy logical system and the adaptation parameters to estimate the model uncertainties and system states directly for using linear analytical results as the system states are unknown or partially known, and the system output is with delay. Based on Lyapunov criterion and linear matrix inequalities method, some sufficient conditions are derived so that all states of the system are uniformly ultimately bounded and the effect of the external disturbance on the tracking error can be attenuated to any prescribed level and consequently an H∞ tracking control is achieved. Finally, a chaotic Chua's circuit system as a simulation example and some comparisons are given to illustrate the validity and effectiveness of the proposed method. - Author(s): C. Desmouliers ; E. Oruklu ; J. Saniie
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 321 –328
- DOI: 10.1049/iet-cds.2010.0259
- Type: Article
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p.
321
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(8)
Designing a universal embedded hardware architecture for discrete wavelet transform is a challenging problem because of the diversity among wavelet kernel filters. In this work, the authors present three different hardware architectures for implementing multiple wavelet kernels. The first scheme utilises fixed, parallel hardware for all the required wavelet kernels, whereas the second scheme employs a processing element (PE)-based datapath that can be configured for multiple wavelet filters during run-time. The third scheme makes use of partial run-time configuration of FPGA units for dynamically programming any desired wavelet filter. As a case study, the authors present FPGA synthesis results for simultaneous implementation of six different wavelets for the proposed methods. Performance analysis and comparison of area, timing and power results are presented for the Virtex-II Pro FPGA implementations. - Author(s): T. Sümesağlam ; R. Song ; G.R. Murray ; A. Guerra
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 329 –333
- DOI: 10.1049/iet-cds.2010.0212
- Type: Article
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p.
329
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(5)
A receiver circuit with built-in electrical overstress protection for a graphics double data rate, version 5 (GDDR5) interface is proposed. The new circuit in a fully functional memory controller system is fabricated in a 45 nm CMOS process using only native thin-gate transistors. The receiver's functionality and performance are experimentally verified at 5.6 Gb/s with 20 ps set-up/hold and 54 mVpp voltage uncertainty with better than 10−12 bit error rate (BER). - Author(s): D. Mondal and K. Biswas
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 334 –342
- DOI: 10.1049/iet-cds.2010.0366
- Type: Article
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p.
334
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(9)
A single-component fractional order element (FOE) is realised and its performance is compared with the conventional FOEs such as cross resistance-capacitance (RC) ladder network and domino ladder network in the analogue domain. The single-component FOE is a capacitive-type probe coated with a porous film of poly-methyl-methacrylate (PMMA) and is dipped in polarisable medium. The fractional exponent of the fabricated single-component FOE and domino ladder can be varied between 0 and 1 whereas that of cross RC ladder realised in this work is 1/2. The performance of fractional order integrator (FOI) using these FOEs is studied in both frequency and time domain by simulation and experimentation. A comparative analysis of the performance of FOI is carried out. - Author(s): S. Chakraborty ; A. Mallik ; C.Kr. Sarkar
- Source: IET Circuits, Devices & Systems, Volume 5, Issue 4, p. 343 –350
- DOI: 10.1049/iet-cds.2010.0299
- Type: Article
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p.
343
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(8)
Analogue circuits based on subthreshold operation of the devices are very attractive as they show significantly better performance in terms of both power dissipation and voltage gain. A systematic investigation, with the help of extensive process and device simulations, of the effects of halo doping [both double-halo and single-halo or lateral asymmetric channel (LAC)] on the subthreshold analogue performance of 100 nm silicon-on-insulator CMOS devices and circuits is reported for the first time. Although the halo doping is found to improve the subthreshold performance in general, the improvement is significant for a low tilt angle of the halo implant. The optimisation of the analogue performance is made for the halo devices by varying the tilt angle of the halo implant. CMOS amplifiers made with the halo-implanted devices are found to have higher voltage gain over their conventional counterpart, and a more than 70% improvement in the voltage gain is observed when both n- and p-channel transistors in the amplifier are LAC devices.
Computing all the Floquet eigenfunctions of oscillators using harmonic balance Jacobian matrices
Start-up circuit with low minimum operating power for microwatt energy harvesters
Loop gain of the common-gate Colpitts oscillator
Design of energy-efficient and robust ternary circuits for nanotechnology
Dynamic power control circuit for implantable biomedical devices
Fuzzy adaptive observer-based control for Chua's circuit with output time delay
Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s
5.6 Gb/s receiver with electrical overstress protection for GDDR in a 45 nm CMOS
Performance study of fractional order integrator using single-component fractional order element
Subthreshold performance of pocket-implanted silicon-on-insulator CMOS devices and circuits for ultra-low-power analogue/mixed-signal applications
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