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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 4, Issue 6, November 2010

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Volume 4, Issue 6

November 2010

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    • Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling
      • Author(s): I.J. Chang ; J. Park ; K. Kang ; K. Roy
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 469 –478
      • DOI:  10.1049/iet-cds.2010.0137
      • Type: Article
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      • p. 469 –478 (10)
        Owing to increase in parametric variations with technology scaling, accurate estimation of bit-cell failure probability in nano-scale static random access memory (SRAM) has become an extremely challenging task. In this study, the authors propose a method to detect the SRAM bit-cell failure, named ‘critical point sampling’. Using this technique, read and hold failure probability of an SRAM bit-cell can be efficiently estimated in a simulation-based way. Simulation results show that our estimation method provides high accuracy, while being ∼50× faster in computational speed compared to transient Monte-Carlo simulation. The method can be applied to optimise SRAM design for better yield and contributes significantly in reducing the overall design time.
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      CMOS class-E power amplifier (1.8-GHz) with an additional thin-film technology
      • Author(s): C. Park  and  C. Seo
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 479 –485
      • DOI:  10.1049/iet-cds.2010.0014
      • Type: Article
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      • p. 479 –485 (7)
        A 1.8-GHz power amplifier is implemented using the 0.18-µm Radio Frequency (RF) Complementary Metal Oxide Semiconductor (CMOS) process. An additional thin-film technology on a separate substrate is used to design the output matching network for high efficiency. To minimise the number of bond-wires, a single differential power stage is used. The output matching network was completed with the proposed load impedance transformer and an Metal Insulator Metal (MIM) capacitor using additional thin-film technology. The amplifier achieved a drain efficiency of 50.5% at a maximum output power of 31.6 dBm at 1.81 GHz.
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      Analysis and design of a high-Q differential active inductor with wide tuning range
      • Author(s): C. Li ; F. Gong ; P. Wang
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 486 –495
      • DOI:  10.1049/iet-cds.2010.0011
      • Type: Article
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      • p. 486 –495 (10)
        The analysis and design of a high-Q differential active inductor with wide tuning range is presented in this study. The self-resonant frequency (SRF) and quality factor (Q) of the inductor can be tuned independently. The inductor was implemented in a 0.13 µm CMOS process. The measured SRF is tunable from 0.5 to 10.2 GHz. The obtained maximum quality factor is as high as 3000. The analysis shows that higher inductance corresponds to higher inductor noise while the correlation between quality factor and noise is relatively weak. Measurement results confirmed these predictions. The measured results show that this inductor structure is suitable for broadband reconfigurable radio-frequency system development. Further analysis and measurements show that the inductor is intrinsically non-linear, so are gyrator-C-based active inductors in general. A compensation circuit is proposed to improve the linearity characteristics of such inductors.
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      Grounded capacitor current mode single resistance-controlled oscillator using single modified current differencing transconductance amplifier
      • Author(s): D. Biolek ; A.Ü. Keskin ; V. Biolkova
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 496 –502
      • DOI:  10.1049/iet-cds.2009.0330
      • Type: Article
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      • p. 496 –502 (7)
        This study proposes a current mode canonical single resistance-controlled oscillator (SRCO) circuit based on a single modified current differencing transconductance amplifier. The circuit employs grounded capacitors and provides a current output with high output impedance. The proposed circuit also enables orthogonal control of frequency and oscillation condition. The performance of the proposed SRCO is verified by means of simulation program with integrated circuit emphasis (SPICE) simulations, on-chip experiments and measurements.
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      Offset voltage estimation model for latch-type sense amplifiers
      • Author(s): S.-H. Woo ; H. Kang ; K. Park ; S.-O. Jung
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 503 –513
      • DOI:  10.1049/iet-cds.2010.0092
      • Type: Article
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      • p. 503 –513 (11)
        A sense amplifier detects a small signal and amplifies it to produce a large signal. However, a sensing failure may occur owing to the offset voltage caused by the mismatch of paired transistors in the sense amplifier. Since the yield of a sense amplifier is the strong function of the offset voltage, estimation of the offset voltage and its statistical distribution is critical in designing sense amplifiers. As offset voltage can be assumed to follow a Gaussian distribution, its standard deviation (1-sigma, σOS) can be estimated from a simple variance model for paired transistors. However, owing to secondary effects such as differential charge injection, drain-induced barrier lowering and stack effect, σOS estimated using the variance model deviates from that obtained from statistical (Monte-Carlo) simulation, and the deviation becomes larger as technology scales down. This study analyses secondary effects on the offset voltage in the most commonly used latch-type sense amplifiers and suggests novel σOS estimation model. The proposed model, which considers secondary effects, can accurately estimate σOS even when technology scales down. This study also presents the trend of the influence of secondary effects on the offset voltage with technology scaling.
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      Field programmable analogue array implementation of fractional step filters
      • Author(s): T.J. Freeborn ; B. Maundy ; A.S. Elwakil
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 514 –524
      • DOI:  10.1049/iet-cds.2010.0141
      • Type: Article
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      • p. 514 –524 (11)
        In this study, the authors propose the use of field programmable analogue array hardware to implement an approximated fractional step transfer function of order (n+α) where n is an integer and 0 < α < 1. The authors show how these filters can be designed using an integer order transfer function approximation of the fractional order Laplacian operator sα. First and fourth-order low- and high-pass filters with fractional steps from 0.1 to 0.9, that is of order 1.1–1.9 and 4.1–4.9, respectively, are given as examples. MATLAB simulations and experimental results of the filters verify the implementation and operation of the fractional step filters.
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      Analytical model for deriving the threshold voltage of a short gate SOI MESFET with vertically non-uniformly doped silicon film
      • Author(s): C.H. Suh
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 525 –530
      • DOI:  10.1049/iet-cds.2009.0307
      • Type: Article
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      • p. 525 –530 (6)
        An analytical model for deriving the threshold voltage of a short gate SOI MESFET in which the silicon film doping density is vertically non-uniform is suggested. Taking into account the lateral variation of the bottom channel potential and using the derived natural length expression, the potentials in both silicon film and buried oxide layer are derived fully two-dimensionally. Making use of them, the minimum bottom channel potential can be obtained to describe the threshold voltage expression in terms of device parameters and applied voltages. Obtained results can be found to explain the drain-induced barrier lowering, drain-induced threshold voltage roll-off and the back-gate effect in a unified manner.
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      Theoretical and experimental determination of onset and scaling of non-quasi-static phenomena for interdigitated fin field effect transistors
      • Author(s): G. Crupi ; D.M.M.-P. Schreurs ; A. Caddemi
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 531 –538
      • DOI:  10.1049/iet-cds.2010.0043
      • Type: Article
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      • p. 531 –538 (8)
        The efficient development of device fabrication and circuit design for microwave applications require a thorough analysis of the microwave performance of the intrinsic transistor with respect to the total gate periphery, since enlarging the transistor channel width allows in obtaining higher levels of output current and gain. Oftentimes, this analysis is carried out by using the intrinsic equivalent circuit elements and their conventional scaling rules. In contrast to that, the purpose of this study is to investigate the scaling of the microwave transistor behaviour directly by using the intrinsic admittance parameters in the microwave frequency range up to 50 GHz. In particular, the scalability and the onset frequency of the non-quasi-static effects for interdigitated fin field effect transistors is theoretically and experimentally analysed against the number of fingers. The results reveal that the onset frequency of the non-quasi-static phenomena is mainly determined by the time constant of the output RC network, which is due to the lossy substrate, and its value is roughly independent of the gate width.
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      A new compact low-offset push–pull output buffer with current positive feedback for a 10-bit LCD source driver
      • Author(s): C.-H. Tsai ; J.-H. Wang ; H.-Y. Zheng ; C.-T. Chang ; C.-Y. Wang
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 539 –547
      • DOI:  10.1049/iet-cds.2010.0119
      • Type: Article
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      • p. 539 –547 (9)
        In this study, a low-offset push–pull output buffer and an area-efficient resistor-capacitor digital-to-analogue converter for a 10-bit liquid crystal display (LCD) source driver are presented. Compared to other push-pull output buffers, the proposed output buffer has a smaller area and lower power consumption. Two complementary push–pull output buffers driving a pair of column lines realise a rail-to-rail driver. The output buffer has strong driving capability with push–pull function by the current positive feedback (CPF). Therefore the source driver can drive the pixel with two-dot inversion to decrease power consumption. On the other hand, the proposed output buffer with CPF can integrate the offset average to reduce the offset voltage. The performance is experimentally verified with a prototype chip that occupies a silicon area of 1700×260 µm2 in a 0.35-µm 2P4M CMOS process. The measured settling time is less than 7.8 µs.
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      Comparison of nano-scale complementary metal-oxide semiconductor and 3T–4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic
      • Author(s): V. Ramesh ; S. Dasgupta ; R.P. Agarwal
      • Source: IET Circuits, Devices & Systems, Volume 4, Issue 6, p. 548 –560
      • DOI:  10.1049/iet-cds.2010.0160
      • Type: Article
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      • p. 548 –560 (13)
        Subthreshold logic has gained wide research interest due to their suitability for ultra low-power applications, such as radio frequency identification, wireless micro sensors and so on, which demand low-energy consumption. Important concerns for subthreshold logic at present are increased sensitivity to process, voltage and temperature (PVT) variations. Analysis is done addressing the nano-scale complementary metal-oxide semiconductor (CMOS) device and circuit subthreshold behaviour to PVT variations, showing their poor performance and robustness in terms of power, delay, energy consumption and so on. Next part of the study addresses how double gate (DG) fin-shaped field-effect transistors (FinFETs) are better candidates for subthreshold logic in comparison to equivalent bulk CMOS devices in terms of robustness. It is observed that DGFinFETs have almost 81% better power performance characteristics than equivalent bulk CMOS option for subthreshold operation. Among the various DGFinFET device options, 3TDG (tied gate DG) device option has better (approximately 77%) energy delay product (EDP) characteristics than 4TDG (independent gate DG) device option for subthreshold operation. Comparative studies show the suitability of symmetric, asymmetric oxide features in combination with tied and independent gate options for subthreshold operation, showing better EDP characteristics of 3TSDG device option and better robustness of 4TSDG device option.
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