Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 4, Issue 3, May 2010
Volumes & issues:
Volume 4, Issue 3
May 2010
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- Author(s): G. Bartolucci ; F. Giannini ; L. Scucchia
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 181 –187
- DOI: 10.1049/iet-cds.2008.0319
- Type: Article
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p.
181
–187
(7)
An analytic model for the design of the elementary cell of the gate circuit in distributed amplifiers is discussed. The used approach is based on the image parameter representation of two-port networks. A closed form expression for the input impedance of the amplifier is provided. Design considerations for the gate circuit are presented based on this analytical result. The simulation of the gate network is performed by means of a commercial software package, including the physical models of the microstrip transmission lines and discontinuities present in the actual structure. Moreover, an hybrid circuit with the same configuration of the gate network has been manufactured. The agreement between experimental numerical and analytical data is remarkable. - Author(s): S. Maheshwari
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 188 –195
- DOI: 10.1049/iet-cds.2009.0259
- Type: Article
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p.
188
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(8)
The author presents a current-mode current-controlled third-order quadrature oscillator circuit synthesised from a simple yet novel approach using basic bilinear blocks. The new circuit is more compact than the other third-order oscillators available in the literature and enjoys non-interactive frequency control, use of grounded capacitors and availability of both quadrature current and voltage outputs. PSPICE simulations are performed for the verification of the new circuit. Experimental evidence is further given for completeness sake. The new basic scheme is also useful for realising a quadrature oscillator using other active elements as well. - Author(s): K.-H. Chen
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 196 –206
- DOI: 10.1049/iet-cds.2009.0242
- Type: Article
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p.
196
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(11)
This study presents a high-throughput deblocking filter accelerator with 48 cycles-per-macro-block processing capability for H.264. This innovation is achieved by considering both luminance data and chrominance data at the same time in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously compute filtering of four edges. Besides, interleaved memory organisation is adopted to eliminate all the data conflicts. This design keeps the data scanning order compliant with that recommended for data communication between modules in H.264 systems. Hence, no interfacing overhead is required for reordering the input and output data. After being implemented by using a 0.18-µm CMOS technology, this work can achieve the real-time performance requirement of 6 K (6000×4000@30 fps) application when operated at 135 MHz frequency at a cost of 41.6 K gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also possesses higher hardware computing efficiency. - Author(s): G. Yu ; Y. Wang ; H. Yang ; H. Wang
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 207 –217
- DOI: 10.1049/iet-cds.2009.0173
- Type: Article
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p.
207
–217
(11)
Design of a fast-locking phase-locked loop (PLL) is one of the major challenges in today's wireless communications. A recently reported digitally controlled oscillator (DCO)-based all-digital PLL (ADPLL) can achieve an ultrashort settling time of 10 µs. This study describes a new DCO tuning word (OTW) presetting technique for the ADPLL to further reduce its settling time. Estimating the required OTW is the most crucial issue for presetting. Two methods are proposed here to estimate the required OTW. One method is using a foreground calibration block to eliminate the effect of DCO gain (KDCO) estimation error (ɛK) and then directly calculating the required OTW for the process/voltage/temperature calibration (PVT-calibration) mode of the ADPLL. The other method is using a new counter-based mode switching controller (CB-MSC) to estimate the required OTW for the acquisition mode and tracking mode. This method is based on the ADPLL's inherent characteristic of frequency toggling and is independent of loop parameters. Furthermore, our proposed presetting technique can be used with the dynamic loop bandwidth control technique together. The ADPLL with the proposed OTW estimating and presetting block is designed using very-high-speed integrated circuit hardware description language and simulated in ModelSim environment. Simulation results demonstrate that a minimum settling time of 2.9 µs is achieved and the improvement is about 40–50% on average compared with the ADPLL without our techniques. - Author(s): F. Colodro and A. Torralba
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 218 –226
- DOI: 10.1049/iet-cds.2009.0106
- Type: Article
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p.
218
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A finite impulse response (FIR) digital-to-analogue converter (DAC) in the feedback path has been shown to reduce the sensitivity to clock jitter of continuous-time sigma-delta modulators (SDMs). A method to analyse the impact of the additional loop delay introduced by the FIR-DAC on the modulator stability is proposed in this paper. This method is applied to the pulse width modulated (PWM) SDM. As in the PWM-SDM the pulse-width modulator is sampled at a frequency higher than the quantiser, a discrete time model is first obtained which operates with only one clock. The stability analysis is based on a linear model with a new criterion which takes into account the quantiser overloading. The theoretical results are in accordance with the results obtained by simulation. Here, it is shown that PWM-SDMs with an order greater than 2 can be designed maintaining the low sensitivity of multiple feedback architectures to a delay in the outer loop. - Author(s): S. Wang ; Z. Zhao ; C. You
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 227 –238
- DOI: 10.1049/iet-cds.2009.0238
- Type: Article
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p.
227
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Piezoelectric materials constitute a class of intelligent materials that are helpful for monitoring the structural integrity. The principle of the piezoelectric impedance-based structural health monitoring technique is to measure the electrical impedance of a piezoelectric patch attached to a structure in a certain frequency range. Electrical impedance variations indicate physical changes in the structure due to the coupling between the electrical impedance and the mechanical impedance. Traditional methods use an impedance analyser that increases the inspection cost. The objective of this work is to introduce an electronic circuit for the piezoelectric impedance-based structural health monitoring. The circuit can monitor the electrical impedance variations of a piezoelectric patch attached to a structure. The frequency range is from 7.47 to 277.29 kHz. This frequency range covers the sensitive range of the piezoelectric structural integrity. The power consumption of the circuit is 18.15 mW. The chip area is 1.03 mm×2.30 mm. The cost of the final design will be much lower than that of an impedance analyser. Using a wireless communication circuit, a sensor network might be established in the future. - Author(s): B. Jiao ; S. Krishnan ; A. Kabbani
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 239 –250
- DOI: 10.1049/iet-cds.2009.0141
- Type: Article
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p.
239
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(12)
A novel field programmable gate array (FPGA) implementation of adaptive segmentation for non-stationary biomedical signals is presented. The design uses Simulink-to-FPGA methodology and has been successfully implemented onto Xilinx Virtex II Pro device. The implementation is based on the recursive least-squares lattice (RLSL) algorithm using double-precision floating-point arithmetic and is programmable for users providing data length, system order and threshold selection functions. The implemented RLSL design provides very good performance in obtaining accurate conversion factor values with a mean correlation above 99% and detecting segment boundaries with high accuracy for both synthesised and real-world biomedical signals. - Author(s): D. Chatterjee and T.W. Manikas
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 251 –260
- DOI: 10.1049/iet-cds.2009.0049
- Type: Article
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p.
251
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The density of chip power dissipation has been increasing steadily over the past several years. High operating temperatures and the existence of hotspots are degrading chip performance and undermining chip reliability. Reducing maximum on-chip temperatures is becoming increasingly important as technology scales below 65 nm. Existing thermal floorplanner compact blocks at the lowest leftmost position allowed by the floor plan encoding. Such compaction minimises chip area but is sub-optimal for wire length and thermal objectives. It is possible to move the blocks in the whitespace (unoccupied chip area) to minimise maximum on-chip temperature without affecting the overall chip area and with a minimal wire length increment of ∼2–3%. However, reallocation of whitespace for thermal optimisation has not been addressed by researchers to date. Here, the development of a constrained particle swarm optimisation algorithm to find an optimal solution to the problem has been described. Simulation results on MCNC benchmark circuits indicate that this method can reduce the maximum on-chip temperature of thermal-aware floor plans by 0.58–7.10°C. - Author(s): M. Alahmad and H. Hess
- Source: IET Circuits, Devices & Systems, Volume 4, Issue 3, p. 261 –268
- DOI: 10.1049/iet-cds.2009.0154
- Type: Article
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p.
261
–268
(8)
In the area of power storage for aerospace applications, Jet Propulsion Laboratory, California Institute of Technology, has developed an all solid-state rechargeable micro-scale lithium ion battery cell (micro-battery) rated at 4.25 V, with nano-Ampere–hour capacity. One of the advantages of this development is the ability to fabricate approximately 20 000 individual micro-battery cells adjacent to each other on the same four-inch silicon wafer. To take advantage of a pre/post-fabricated series, parallel or series/parallel connection of the cells, a power management system has been developed and sub-system circuits designed using a combination of device and circuit techniques meeting high voltage switching requirements in silicon on insulator (SOI) technology to reconfigure and control the charge/discharge operation of the cells for practical application. This study will present a detailed analysis of the power management system and its sub-circuit components. The circuit components have been simulated using 3.3 V SOI SPICE models and have been fabricated in a 0.35 µm Microwave SOI process. A description of the system and the results will also be discussed and analysed.
Design considerations for the gate circuit in distributed amplifiers
Current-mode third-order quadrature oscillator
48 Cycles-per-macro block deblocking filter accelerator for high-resolution H.264/AVC decoding
Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting
Impact of finite impulse response digital-to-analogue converter delay on the stability of continuous-time sigma-delta modulators with pulse-with modulation in the feedback path
0.18 µm CMOS integrated circuit design for impedance-based structural health monitoring
FPGA implementation of adaptive segmentation for non-stationary biomedical signals
On-chip thermal optimisation by whitespace reallocation using a constrained particle-swarm optimisation algorithm
Microwave silicon on insulator-based design of a power management system for Jet Propulsion Laboratory's rechargeable micro-scale batteries
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