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Online ISSN 1751-8598 Print ISSN 1751-858X

IET Circuits, Devices & Systems

Volume 3, Issue 3, June 2009

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Volume 3, Issue 3

June 2009

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    • Low power design of CMOS 5-GHz voltage-controlled oscillator from narrowband to wideband with switching capacitor module
      • Author(s): M.-T. Hsu ; C.-T. Chiu ; S.-H. Chen
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 3, p. 99 –105
      • DOI:  10.1049/iet-cds.2008.0300
      • Type: Article
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      • p. 99 –105 (7)
        In this study, we demonstrated low power and low phase noise of the complementary cross-coupled voltage-controlled oscillators (VCOs). Two chips are implemented by TSMC standard 0.18-µm Complementary Metal-Oxide Semiconductor (CMOS) process. The first one that employed a memory reduction tail transistor technique is operated from 5.17 to 5.85 GHz at a supply voltage of 1.2 V whereas its tuning range is 12.3%. The power consumption is 1.8 mW whereas the measured phase noise is −126.6 dBc/Hz at 1-MHz frequency offset from 5.17 GHz. The other employed switching capacitor modules to achieve wide tuning range and minimise phase noise, it operated from 3.64 to 5.37 GHz with 38% tuning range. The power consumption is 13.7 mW by a 1.8 V supply voltage and the measured phase noise in all tuning ranges is less than −122 dBc/Hz at 1-MHz frequency offset.
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      Analogue signal processing applications using a new circuit topology
      • Author(s): S. Maheshwari
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 3, p. 106 –115
      • DOI:  10.1049/iet-cds.2008.0294
      • Type: Article
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      • p. 106 –115 (10)
        New circuit topology for realising simple voltage-mode analogue functions, using one differential voltage current conveyor with positive output and a maximum of three passive elements, is proposed. The new topology can realise nine circuits including amplifier, integrator, differentiator and first-order all-pass filters. All the circuits show wide linearity, low total harmonic distortion (THD) and a simple realisation. Non-ideal and parasitic study is also given. As application examples, the new analogue blocks are used in realising biquad filter and third order quadrature oscillator. The proposed theory is validated by PSPICE simulation results as well as experimental results using AD844s. The catalogue of simple circuits along with their applications makes the work a future prospect for adoption to IC implementation by analogue IC producers.
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      Highly efficient CAVLC encoder for MPEG-4 AVC/H.264
      • Author(s): T.-H. Tsai ; S.-P. Chang ; T.-L. Fang
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 3, p. 116 –124
      • DOI:  10.1049/iet-cds.2008.0231
      • Type: Article
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      • p. 116 –124 (9)
        In dealing with high-resolution video information, encoding (or decoding) with an efficient context-based adaptive variable length code (CAVLC) encoder is important. A highly efficient CAVLC encoder is proposed for video coding application of MPEG-4 AVC/H.264. The main concept is to use block-based pipelining to speed up encoding efficiency and reduce the pipeline storage elements by using the associated input buffer. We also use zero-block detection to speed up encoding efficiency and eliminate the same codeword from all the tables to save the hardware cost. Simulation results show that our design can meet the real-time processing for 1920×1088 resolution with lower operation frequency. We also accomplish the higher encoding throughput with a more complete CAVLC design than others. The proposed design has been implemented and synthesised with TSMC 0.18 µm standard cell library. The synthesis result indicates that the gate count is 12 125 with the clock constraint of 125 MHz.
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      Controllable readout circuit for indium gallium arsenide photodiode array applications
      • Author(s): Y.-S. Hwang ; S.-C. Wang ; B.-P. Lai ; J.-J. Chen
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 3, p. 125 –134
      • DOI:  10.1049/iet-cds.2008.0343
      • Type: Article
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      • p. 125 –134 (10)
        This study presents a controllable integration time readout integrated circuit (ROIC) with a 32 by 32 indium gallium arsenide (InGaAs) detector array. This ROIC is designed for InGaAs photodiode (PD) array detectors to operate at low input current and is suitable for the focal plane array (FPA) in near infrared (NIR) field. The integration time of this ROIC can be controlled by an external clock pulse, and is adjustable from 0.5 µs to infinity by varying the light intensity. Moreover, the pre-stage of ROIC is based on the buffer gate modulation input (BGMI) architecture with differential structure and a double delta sampling (DDS) circuit, providing better sensitivity, a wider dynamic range, a higher injection efficiency and reduced noise. Further, because this ROIC is built into a sample-and-hold circuit in the unit cell, it can operate in the full frame snapshot mode. The proposed ROIC has 1024 pixels and a 30-µm pixel pitch. It is implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm Complementary Metal-Oxide-Semiconductor (CMOS) process with a 5-V power supply. The output swing is over 2.2 V. It has ±5% non-linearity, 91.559 mW chip power dissipation and a chip area of 1.628×2.341 mm2 without pads.
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      Development of ultra wideband, high efficiency, distributed power amplifiers using discrete GaN HEMTs
      • Author(s): S. Lin ; M. Eron ; A.E. Fathy
      • Source: IET Circuits, Devices & Systems, Volume 3, Issue 3, p. 135 –142
      • DOI:  10.1049/iet-cds.2008.0339
      • Type: Article
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      • p. 135 –142 (8)
        This study describes the design and performance of a discrete ultra wideband GaN HEMT distributed power amplifier (DPA) with over 5 W (37 dBm) output power and a PAE exceeding 27% in the 0.02–3 GHz frequency range. The implemented DPA design is comprised of three discrete GaN HEMT devices. Its performance was enhanced using tapered drain lines and non-uniform gate capacitive coupling. The design methodology is based on both small and large signal analysis using harmonic balance technique, and their associated predicted and experimental results are discussed here in detail.
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