Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 3, Issue 2, April 2009
Volumes & issues:
Volume 3, Issue 2
April 2009
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- Author(s): V. Riewruja and T. Kamsri
- Source: IET Circuits, Devices & Systems, Volume 3, Issue 2, p. 57 –63
- DOI: 10.1049/iet-cds.2008.0140
- Type: Article
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p.
57
–63
(7)
A method for implementing square-rooting and absolute function circuits using operational amplifiers (opamps) as only active elements is introduced. The realisation technique is provided through the use of the opamp supply-current sensing, which utilises an inherently quadratic characteristic of the opamp class-AB output stage. The proposed circuits are attractive in terms of simple configuration and low cost. The performances of the circuits are discussed in detail. Experimental results demonstrating the characteristics of the circuits using commercially available opamps are also included. - Author(s): S. Eachempati ; N. Vijaykrishnan ; A. Nieuwoudt ; Y. Massoud
- Source: IET Circuits, Devices & Systems, Volume 3, Issue 2, p. 64 –75
- DOI: 10.1049/iet-cds.2008.0149
- Type: Article
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p.
64
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(12)
The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54% improvement in area-delay product over the best performing architecture with standard copper interconnect in 22 nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43% over FPGAs implemented using traditional copper interconnect in future process technologies. - Author(s): M. Chan and A. Postula
- Source: IET Circuits, Devices & Systems, Volume 3, Issue 2, p. 76 –82
- DOI: 10.1049/iet-cds.2008.0119
- Type: Article
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76
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This work gives insight into the behaviour of second-order bang–bang phase locked loops in the far from lock region. This region, while largely unexplored, is of particular interest as PLL behaviour in this region determines locking time and capture range. By analysing PLL cycle slipping behaviour in this region, the transient response for the system is derived. Expressions for first-order system stability and locking time are also presented. - Author(s): M.-D. Shieh ; T.-P. Wang ; D.-W. Yang
- Source: IET Circuits, Devices & Systems, Volume 3, Issue 2, p. 83 –90
- DOI: 10.1049/iet-cds.2008.0262
- Type: Article
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83
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Register exchange (RE) structures are commonly applied to survivor memory design for Viterbi decoders aiming at high-speed, low-latency requirements. The authors explore low-power RE survivor memory architectures based on the trace-forward concept. When trace-forward units (TFUs) are used to derive decoded outputs instead of pointing to merged states in trace-back applications, we have the freedom of selecting the length of TFUs for obtaining different segmented RE (SRE) structures. Using the inherent properties in the TFU and properly setting the initial values of registers in SRE structures, a significant saving in power dissipation and a reduced number of RE stages can then be achieved. Experimental results exhibit that about 54% savings in power can be obtained using our development compared to conventional RE structures. - Author(s): V. Issakov ; M. Wojnowski ; A. Thiede ; L. Maurer
- Source: IET Circuits, Devices & Systems, Volume 3, Issue 2, p. 91 –98
- DOI: 10.1049/iet-cds.2008.0276
- Type: Article
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p.
91
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Accurate radiofrequency (RF) characterisation of on-chip or on-board devices often requires de-embedding to account for parallel and serial parasitics associated with bonding pads and interconnects. It is usually performed by well-known techniques such as Open-Short, Pad-Open-Short or Thru. However, these approaches or alternative techniques employing more standards assume a specific lumped-element model of bonding structures. This reduces de-embedding accuracy at higher frequencies. The Thru de-embedding technique is analysed in this paper and it is shown that under certain conditions de-embedding can be performed without modelling of the internal structure of the thru standard. The possibility to obtain the parameters of an error network by using a single test structure reduces significantly the costs of manufacturing standards and saves the measurement time. Further, an extension of the Thru technique is introduced. It is shown that at the expense of one more measurement, it is possible to characterise the system without additional assumptions. The presented method can be applied, for example, for de-embedding of fixtures with different connectors on either side. Additionally, the extension of Thru technique for de-embedding of differential devices is proposed. The paper verifies the extension for asymmetrical structures by simulation performed using Sonnet electromagnetic field solver in the frequency range 1–40 GHz. Finally, the extension for differential devices is verified by measurement in the frequency range 1–20 GHz and comparison of the results with Open-Short de-embedding technique.
Square-rooting and absolute function circuits using operational amplifiers
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect
Transient analysis of bang–bang phase locked loops
Low-power register-exchange survivor memory architectures for Viterbi decoders
Extension of Thru de-embedding technique for asymmetrical and differential devices
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