Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 2, Issue 2, April 2008
Volumes & issues:
Volume 2, Issue 2
April 2008
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- Author(s): B. Parhami
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 179 –186
- DOI: 10.1049/iet-cds:20070235
- Type: Article
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p.
179
–186
(8)
A scheme is proposed for representing 2's-complement binary numbers in which there are two least-significant bits (LSBs). Benefits of the extra LSB include making the number representation range symmetric (i.e. from −2k−1 to 2k−1 for k-bit integers), allowing sign change by simple bitwise logical inversion, facilitating multiprecision arithmetic and enabling the truncation of results in lieu of rounding. These advantages justify the added storage and interconnect costs stemming from the extra bit. Operation latencies show little or no change relative to conventional 2's-complement arithmetic, thus making double-LSB representation attractive. - Author(s): L. Xie and A. Davoodi
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 187 –200
- DOI: 10.1049/iet-cds:20070189
- Type: Article
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p.
187
–200
(14)
A fast and accurate statistical static timing analysis approach is presented, which supports skewed non-Gaussian process parameter variations. First, the authors propose modelling of non-Gaussian sources of variation using a skew-normal random variable that can represent a large class of non-Gaussian distributions such as log-normal and Poisson. Secondly, the authors present a linear gate delay model in terms of skew-normal as well as Gaussian parameters. The high accuracy of the linear model is discussed and verified using Spice simulations. Thirdly, the authors approximate arrival time expressions as skewed (and not skew-normal) random variables in an effort to quickly capture their shapes without loss of accuracy. A proposed linear representation of skewed arrival times enables computing the exact analytical expression for the MAX of arrival times as well as for their first three moments, which can be evaluated in an efficient manner. Overall, the calculation of the MAX operation is done efficiently (i.e. comparable to the solely linear-Gaussian case) with high accuracy and restriction-free for a realistic representation of non-Gaussian process parameters. - Author(s): B. Maundy ; S. Gift ; P. Aronhime
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 201 –206
- DOI: 10.1049/iet-cds:20070164
- Type: Article
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p.
201
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(6)
A novel voltage- or current-controlled grounded resistor is proposed. The circuit makes use of bisection of the drain-to-source voltage of a field effect transistor to produce a practical linear resistor with dynamic range extension. A second generation positive current conveyor is used with three resistors to extend the linearity of the variable resistor, and the resistance can be controlled by a variety of methods. Experimental and PSPICE simulation results, using an AD844 current feedback amplifier and a 2N5485 N-channel JFET, are presented which verify the theoretical derivations. In one experiment, the measured input resistance of the grounded resistor was observed to vary from 1.8 to 18 kΩ or by a factor of ten. - Author(s): R. Mita ; G. Palumbo ; P.G. Fallica
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 207 –212
- DOI: 10.1049/iet-cds:20070180
- Type: Article
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p.
207
–212
(6)
An accurate model useful for simulating single-photon avalanche diodes including biasing circuits is presented. The authors developed the model using Verilog-A codes to describe both static and dynamic behaviours. The derived model fits experimental results extracted from practical devices better than the one used in the open literature. SPECTRE simulations confirmed the validity of the proposed model, which avoids convergence problems and also shows a higher accuracy than traditional models. - Author(s): I. Manić ; S. Djorić-Veljković ; V. Davidović ; D. Danković ; S. Golubović ; N. Stojadinović
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 213 –221
- DOI: 10.1049/iet-cds:20070173
- Type: Article
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p.
213
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(9)
The effects of spontaneous recovery on threshold voltage and channel carrier mobility in DC gate bias stressed power VDMOSFETs, as well as the underlying changes in gate oxide-trapped charge and interface trap densities, are analysed in terms of the mechanisms responsible. Various mechanisms, including drift of oxide-trapped charge to the SiO2–Si interface, charge neutralisation, interface trap redistribution and electrochemical reactions near the interface are considered, in order to explain the experimental results. A major difference in the results for post-stress recovery obtained by subthreshold midgap and single transistor mobility techniques, both indicating mostly decrease in interface trap and oxide-trapped charge densities and the charge pumping technique, which signified a remarkable post-stress increase of true interface trap density, is ascribed to both interface trap redistribution within the silicon bandgap and to the inability of the former two techniques to assess the contribution of border traps to the estimated densities of interface traps. Drift of positive oxide charge to the interface, accompanied by subsequent charge neutralisation and interface trap redistribution, is found to dominate in the early stage of post-stress recovery, whereas the chain of electrochemical reactions involving hydrogen species (passivation of interface traps, dissociation of interfacial trap precursors, hydrogen dimerisation and cracking at charged oxide traps) is shown to become more important in the advanced stage of recovery. - Author(s): Y.-B. Gu ; S.-F. Yueh ; T.-W. Chang ; K.-C. Huang
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 222 –226
- DOI: 10.1049/iet-cds:20070211
- Type: Article
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p.
222
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(5)
A voltage reference with two outputs is presented. Both of them are insensitive to temperature, supply voltage and threshold voltage. One of the outputs is ∼0.8 V, and the other one is ∼0.38 V. For the output voltage of 0.8 V, this voltage variation because of supply voltage change from 2.0 to 3.5 V is ±0.66%, and because of temperature change from 0 to 80°C is ±52 ppm/°C. For the output voltage of 0.38 V, this voltage variation because of supply voltage change from 2.0 to 3.5 V is ±1.8%, and because of temperature change from 0 to 80°C is ±50 ppm/°C. The active area of the circuit is ∼0.021 mm2, and the power consumption for the supply voltage of 2 V is 0.8 mW. - Author(s): W. Aloisi ; G. Palumbo ; S. Pennisi
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 227 –233
- DOI: 10.1049/iet-cds:20060188
- Type: Article
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p.
227
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(7)
Current buffers/amplifiers are used in series to the Miller compensation capacitor with the aim of eliminating the positive zero introduced by the forward path. They are increasingly adopted because of their low-voltage features, high-speed performance and, recently, for their suitability to be used with large capacitive loads (when a current gain is introduced). The authors propose a novel and simple design approach for the frequency compensation of a two-stage amplifier exploiting a current buffer/amplifier. The procedure has been profitably applied to a class-AB two-stage CMOS operational transconductance amplifier, having a 100 pF load. In particular, three compensation networks were designed using a 1.3 pF, 0.6 pF and 250 fF compensation capacitor alternatively. Moreover, the adopted compensation topology provides an improvement in terms of power supply rejection ratio, which was also analytically demonstrated. Simulations that are in very good agreement with theoretical results are also given. - Author(s): S. Maheshwari
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 234 –242
- DOI: 10.1049/iet-cds:20070158
- Type: Article
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p.
234
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(9)
Two new first-order, current-mode all-pass sections, each with high output impedance and requiring only two grounded passive components along with a differential voltage current conveyor, are presented. The new circuits require no matching conditions for the realisation of current transfer functions and are simpler than most of the recently available circuits. The effect of parasitics and non-idealities is also considered. PSPICE simulations using 0.5 µ CMOS parameters confirm the validity and practical utility of the proposed circuits. A typical application in realising a new current-mode quadrature oscillator is given. A four-phase quadrature oscillator with high impedance outputs is also given. - Author(s): E.M. Spinelli ; M.A. Mayosky ; C.F. Christiansen
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 243 –248
- DOI: 10.1049/iet-cds:20070280
- Type: Article
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p.
243
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(6)
Fully differential (F-D) analogue circuits are usually designed focusing only on their differential-mode (DM) behaviour, without considering common-mode (CM) responses. A technique is presented for the design of both DM and CM circuit responses, using fully balanced operational amplifiers (FBOAs) as analogue building blocks. FBOAs work with CM and DM voltages as a whole, having an ideally infinite gain for both modes. This allows independent design of CM and DM dynamics. Inverting and non-inverting F-D topologies can be implemented in a simple way, similar to the implementation of their single-ended counterparts. Some typical application circuits are analysed and discussed and, as a design example, a ‘double-mode oscillator’ (a circuit that has independent CM and DM oscillations) was built and experimentally evaluated. - Author(s): A. Carlosena and A. Mànuel-Lázaro
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 249 –256
- DOI: 10.1049/iet-cds:20070065
- Type: Article
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p.
249
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(8)
The analysis and design of high-order phase-locked loops (PLLs) is difficult. A novel approach is presented which allows high-order loops to be viewed as a natural extension of lower-order ones. Type I low-order PLLs are considered a starting point for the design of higher type, higher-order PLLs. Starting with lower-order PLLs not only permits a comprehensive classification of all practical kinds of PLLs but also facilitates their design from a more intuitive perspective. The model presented, based on the loop filter composed of several nested first-order feedback loops, has been implemented and tested in Simulink®, confirming the ideas presented. - Author(s): S.-C. Lee ; S.-Y. Lee ; C.-H. Chiang
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 257 –263
- DOI: 10.1049/iet-cds:20070163
- Type: Article
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p.
257
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(7)
A 0.9 V fully differential switched-opamp-based sixth-order switched-capacitor bandpass filter, which has frequency response centred at 1.118 kHz with a Q of 0.235 and power saving by a proposed low-power biquad structure, is designed for electroneurography acquisition systems. It is implemented in a 0.18 µm CMOS technology with a normal threshold voltage of 0.48 V. The measured peak signal-to-noise ratio is 52 dB at 1 kHz sinusoid wave with input amplitude of 1 Vpp. In addition, the measured power-supply rejection ratio and common-mode rejection ratio are >40 dB in the desired bandwidth and have peak values of 70 and 67 dB, respectively. A dynamic range of 50 dB for total harmonic distortion of 3% is obtained while dissipating 262 µW and occupying a chip area of 0.35 mm2. - Author(s): N. McNeill and N.K. Gupta
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 265 –276
- DOI: 10.1049/iet-cds:20070226
- Type: Article
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p.
265
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Advantages of using a current transformer (CT) for current sensing in switched mode power converters are that galvanic isolation is inherent, losses are low, the bandwidth is high and a high-amplitude output signal may be obtained. However, ‘droop’ occurs as a result of the magnetising current drawn. Peak current droop is defined as the instantaneous per-unit shortfall in sensed current at the end of a rectangular pulse. Average current droop is defined as the per-unit shortfall in the average current sensed. The CT inherently operates in a resonant mode when sensing a unidirectional current pulse. This is advantageous as some of the current–time product lost to the magnetising branch may be recovered thereby alleviating the average current droop. Average current droop is investigated when diode rectification is used. Three operating modes are identified and described. These are designated the discontinuous magnetising current, continuous magnetising current and discontinuous secondary current modes (DSCM). It is shown that the CT's core losses may predominately influence the average current droop. Provided the DSCM is avoided, simple correction factors are shown to be appropriate for substantially correcting the sensed current to allow for these losses. - Author(s): W. Sun ; H. Li ; Y. Yi ; H. Wu ; L. Shi
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 277 –280
- DOI: 10.1049/iet-cds:20070279
- Type: Article
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p.
277
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(4)
A 192-channel data driver IC for plasma display panel has been proposed using bulk-silicon CDMOS (CMOS and DMOS) technology. A novel latch-up protection structure and a novel high-voltage pLDMOS are used in the data driver IC, so as to avoid the latch-up during the system application and to reduce the process cost by more than 10% compared with the conventional one. The power consumption of the presented data driver IC with a novel level-shift circuit was reduced by >20% compared with the conventional one. The rise and the fall times of the output stage are ∼80 and 104 ns, respectively. - Author(s): T. Kim ; Y. Jeong ; K. Yang
- Source: IET Circuits, Devices & Systems, Volume 2, Issue 2, p. 281 –287
- DOI: 10.1049/iet-cds:20070135
- Type: Article
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p.
281
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(7)
The low-power/high-speed performance of current-mode logic (CML) D flip-flops based on negative-differential-resistance (NDR) devices is presented. The device count used in the fabricated circuit has been significantly reduced by using the NDR-based D flip-flop topology, leading to enhanced low-power/high-speed performance. The operation of the fabricated NDR-based CML D flip-flop has been confirmed to 36 Gb/s, which is the highest speed among NDR-based differential‐mode D flip-flops reported to date. The power consumption of the D flip-flop core circuit was measured to be as low as 20 mW at a power supply voltage of −3.3 V. In addition, a power–delay product of 0.55 pJ has been obtained from the NDR-based CML D flip-flop, which is the lowest value to the authors' knowledge among the previously reported D flip-flops up to operation speeds in the region of 40 Gb/s.
Double-least-significant-bits 2's-complement number representation scheme with bitwise complementation and symmetric range
Fast and accurate statistical static timing analysis with skewed process parameter variation
Practical voltage/current-controlled grounded resistor with dynamic range extension
Accurate model for single-photon avalanche diodes
Mechanisms of spontaneous recovery in DC gate bias stressed power VDMOSFETs
CMOS voltage reference with multiple outputs
Design methodology of Miller frequency compensation with current buffer/amplifier
High output impedance current-mode all-pass sections with two grounded passive components
Dual-mode design of fully differential circuits using fully balanced operational amplifiers
General method for phase-locked loop filter analysis and design
0.9 V low-power switched-opamp switched-capacitor bandpass filter for electroneurography acquisition systems
Assessment of the error in the average current sensed by the unidirectional current pulse transformer
Bulk-silicon power integrated circuit technology for 192-channel data driver ICs of plasma display panel
Low-power high‐speed performance of current-mode logic D flip-flop topology using negative-differential-resistance devices
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