Here, based on Mitchell's logarithmic conversion, the authors propose a fast calibration method using a fixed binary code with case judgement, which suppresses the conversion error. The authors developed a highly paralleled circuit serving the proposed calibration method. Differential cascade voltage switch logic (DCVSL) is used to work in both high-speed logic and adiabatic logic and trade-off between power dissipation and operation speed. In addition, a low-cost adiabatic clock generator without any passive component is presented to support a four-phase sine clock for the adiabatic logic operation. An 8-bit logarithmic converter is designed in TSMC 180 nm CMOS. Post-simulation results show that the proposed calibration can reduce the conversion error to 1.55% based on Mitchell's algorithm, the power dissipation varies between 1.12 and 3.709 mW, and the delay is 1.82 ns under operational DCVLS.

Here, the authors studied a silicon–germanium (Si_1−x Ge _x ) absorber layer for the design and simulation of an ultra-thin crystalline silicon solar cell using Silvaco technology computer-aided design. Seeking ways to design and fabricate solar cells using 100 μm thicker silicon substrates is the subject of intense research efforts among the photovoltaic (PV) community. The aim is to further reduce the substrate thickness to 20 μm without compromising the efficiency of the solar cell. A thin layer of SiGe film with the Ge composition of 15% has been introduced in this work that assists in absorbing the longer wavelength of the sunlight spectrum. The effects of the doping concentration and absorber layer thickness on the conversion efficiency have been examined. The simulated results exhibited significant enhancement in the sunlight absorption as compared to the reference structure based on crystalline silicon. The highest efficiency of 16.8% with an overall solar cell thickness of ∼26 μm has been observed. The proposed heterostructure solar cell design will support the industrial development of an efficient, low-cost, shorter energy payback time, and light-weight PV technology for its widespread implementation.

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over for trinomials. Consequently, an m-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area-delay product, respectively, for m = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.

This study proposes the complementary metal–oxide–semiconductor (CMOS)-based current-mode high-order active low-pass (LP) and band-pass (BP) filters using biquad functions. The passive RLC Chebyshev ladder filters were used as the prototype, and the mesh- and nodal-analysis methods to derive the biquad functions. The CMOS-based transistor-level biquad circuits were subsequently realised from the biquad functions. The high-order active LP and BP ladder filters were then synthesised from an amalgamation of the biquad circuits. Simulations were carried out to verify the performance and functionality of the LP and BP ladder filters. The results revealed that the proposed ladder filters were operable in the high-frequency range and electronically tunable, given a low-voltage supply of 1 V for the entire circuit. The proposed filters could also achieve the LP frequency response of 300 kHz–30 MHz and BP centre frequency of 200 kHz−20 MHz by means of the bias current (I _B) manipulation from 1 to 100 µA. Moreover, the multi-tone simulations were undertaken to assess the filtering performance of the proposed filters and the results are agreeable with the design specifications.

This study introduces a frequency modulated ultra-wideband (FM-UWB) receiver optimised for low power and fast start-up. The receiver consists of a front end amplifier converting a frequency modulated signal to an amplitude modulated signal which is applied to an envelope detector. The receiver front end is for 500 MHz channels centred at 3450 and 3950 MHz. The amplifier uses passive gain and four cascaded gain stages to achieve high radio-frequency gain without the need for super-regeneration. By simplifying the architecture this way, the front end has a 5 μs wake-up time to enable efficient duty-cycling. The measured front end receives a signal at −68 dBm while consuming 600 μW of power (excluding a test buffer) from a 1 V supply. Fabrication was done using the IBM 130-nm CMOS technology on a 1 mm × 1 mm loose die.

Analytical Verilog-A compatible 2D model including quantum short channel effects and confinement for the potential, threshold voltage and the carrier charge sheet density for symmetrical lightly doped double-gate metal-oxide-semiconductor field effect transistors (MOSFETs) is developed. The proposed models are not only applicable to ultra-scaled devices but they have also been derived from 2D Poisson and 1D Schrödinger equations including 2D electrostatics, in order to incorporate quantum mechanical effects. Electron and hole quasi-Fermi potential effects were considered. The models are continuous and have been verified by comparison with COMSOL and BALMOS numerical simulations for channel lengths down to 7 nm at 1 nm oxide thicknesses; very good agreement within ±5% has been observed for silicon thicknesses down to 3 nm.

A low-distortion, low-voltage transconductor based on Nauta's inverter-type transconductor is proposed. The transconductor's core MOSFETs are pushed into a strong inversion region under a low-voltage supply utilizing a level shifter consisting of a linear resistor and a MOSFET current source. The transconductor's linearization relies on summing a decreasing G_m characteristic with an increasing counterpart to obtain an overall flat G_m characteristic. The non-ideal decreasing G_m is exploited from a non-linear behaviour of the triode–MOS current source that restricts a |V _GS| increment of the core strongly-inverted MOSFET quartet while its increasing-G_m counterpart found in another weakly-inverted auxiliary MOSFET quartet. The MOSFET current source plays significant role in the linearization process where it has to be in a triode mode of either a strong, weak or moderate inversion region. Simulation results are provided to verify the feasibility of the proposed transconductor with a 5th-order Chebyshev lowpass filter in a 0.18 µm CMOS process. The filter operates under a 0.5 V supply (the ratio V _DD/V _TH = 1.19) with a continuous bandwidth tuning from 500 kHz to 2.8 MHz. The proposed filter with a nominal 1.4 MHz bandwidth and a 430 mW power consumption renders the two-tone SFDR of 64.9 dB.

Optimal design of digital rational approximations with α-dependant coefficients to model the fractional order integrator of any arbitrary order α, where α ε (0, 1), is presented in this work. The analytical expressions of the coefficients for the proposed fractional order digital integrators (FODIs) are derived by a two-step method: (a) the coefficients of FODIs for α varying from 0.01 to 0.99 in steps of 0.01 are determined by a meta-heuristic optimisation algorithm called symbiotic organisms search (SOS) and (b) curve fitting is applied on the SOS-optimised coefficients to obtain their generalised expressions. Previous works dealing with the design of FODI based on various meta-heuristic optimisers have considered only a few specific fractional orders; hence, the practical usability of such designs is restricted. This gap provides the motivation for conducting this research. Design quality robustness and convergence consistency of SOS are extensively compared with three other well-known meta-heuristic algorithms. The superior modelling accuracy of the proposed designs is justified by comparing with the recent literature. Simulation results validate the effectiveness of the proposed models as a fractional order proportional–integral controller.

In this study, an analytical model for linearly modulated work-function-based delta-doped single-gate tunnel field-effect transistor (TFET) has been developed to improve the analogue performance. The impact of delta-doped layer and linearly modulated metal gate on different analogue parameters has been investigated extensively. The insertion of heavily doped delta layer in the source region improves ON current and current switching ratio performance significantly as compared to conventional TFET. Similarly, the presence of spatially work-function modulated metal gate reduces subthreshold swing and improves performance. The distance of the delta layer from the source–channel interface is optimised to 3 nm to maximise efficiency. The proposed model exhibits much improved analogue performance as compared to conventional TFET and delta-doped TFET. Thus, the model can be viewed as one of the potential replacements for metal–oxide–semiconductor field-effect transistors in ultra-low-power applications. However, the precision of present model is corroborated by using the two-dimensional TCAD Sentaurus simulator.

A source follower with improved output resistance is proposed. This improvement is achieved using shunt–shunt feedback with the help of a voltage combiner in the feedback loop which helps not only enhancing the gain but achieving reduced distortion due to improved isolation. A high-performance Sallen–Key biquad is implemented using this improved source follower and two capacitors which offer 29.3 MHz of bandwidth and almost 50 dB of stopband attenuation with the power of 2.3 mW. A fourth-order Chebyshev low-pass filter prototype is designed with a cascade of two such biquads in 45 nm complementary metal–oxide–semiconductor (CMOS). A cut-off frequency of 12.4 MHz is obtained with a stopband rejection of more than 83 dB. The power dissipation of the filter is 5.1 mW, at 1.2 V supply, and achieves an in-band third-order intercept point of +26.8 dBm. The in-band input-referred noise is , resulting in a dynamic range of 78.1 dB.

Parallel connection of power metal oxide semiconductor field effect transistors (MOSFETs) is often used in the high current side of power conversion systems to obtain a thermal dispersion and low conduction losses. However, a parallel connection may lead to a current unbalance due to the difference of parasitic parameters and switching characteristics of the paralleled devices. The current unbalance generates current oscillations, and in the worst case, it may lead to complete destruction of the power devices. This study analyses an inherent oscillation of two paralleled SiC MOSFETs, under current unbalance conditions. Based on the proposed analysis, it is found that the parasitic inductance is the main cause of the coupled oscillation, which is composed of two different oscillation frequencies. In this study, the coupled oscillation leads to a difference of peak currents between paralleled devices. The circuit conditions, considering the parasitic inductances, are investigated to suppress the coupled oscillation. As a result, a reduction of the common parasitic inductance allows preventing the coupled oscillation and to suppress the peak combined current of paralleled devices. Moreover, a peak current reduction by 37.8% can be achieved, as a result of eliminating the coupled oscillation.

This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 µm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.

A method to determine the pth-order inverse of the Volterra series of multiple-input multiple-output non-linear dynamic systems is presented; it combines time- and frequency-domain techniques to determine the Volterra series of the inverse as a function of the forward system's Volterra series. The method can be used for continuous and discrete time systems. Each operator of non-linear order n of the inverse is a function of the forward system's operators of non-linear order n and lower. It is shown that the p th-order post-inverse is equal to the pth-order preinverse. For the special case that there are no linear cross terms and that the linear memory effects are negligible the kernels of the forward and inverse models are approximately the same. In an example, an approximate inverse model of a model of a concurrent dual band radio frequency amplifier is derived.

Vector rotation is an important component of algorithms in digital signal processing and robotics. Often, the rotation does not require very high accuracy. This study presents a lowoverhead sign-precomputation-based architecture for approximate rotation using the coordinate rotation digital computer (CORDIC) algorithm. The proposed architecture is independent of Z-datapath, and involves precomputation of the direction of rotation for each micro-rotation angle. The approach involves selecting the optimal micro-rotation angles from a set of elementary angles in run time. Careful selection and elimination of the redundant micro-rotation angles leads to a maximum of three iterations for a majority of the input angles while also simultaneously reaching within 0:45 (of the desired rotation angle). An field programmable gate array (FPGA) implementation of the proposed rotation mode CORDIC on XC7K70T-3FBG676 Kintex-7 using Xilinx ISE 13.2 achieves roughly 50% reduction in slice-delay product and power-delay product compared to recent designs. An application of approximate rotation to Hough transform-based lane detection is presented. An efficient algorithm for generation of vote addresses in the parameter space is proposed. It is shown that accurate lane detection is possible along with resource savings using the proposed CORDIC. The proposed architecture reduces the number of additions roughly by a factor of 20 compared with the conventional method of computing a parameter for each feature point.

Modular adders are very crucial components in the performance of residue number system-based applications. Most of the work published so far has been restricted to modulo adders or modulo-specific adders. Less work has been dedicated to modulo-generic adders. This work presents new designs for modulo adders, where K is any integer in the range of . The proposed structure merges two binary adder structures and maximises sharing of components, wherever possible. This merger permits shorter cell-interconnections, which results in space wastage reduction. Additionally, tristate-based multiplexers (MUXs) are used in lieu of the more demanding gate-based MUXs. As examined over a very practical range of n, , and based on a 65 nm VLSI realisation, the circuit layouts of the proposed adders outperform considerably the most recent and competitive functionally identical published works. On average, the proposed designs have shown reductions in area, time, power, and energy of 23.7, 13.8, 22.9, and 33.6%, respectively.

Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose–Chaudhuri–Hocquenghem (BCH) codes and outer Reed–Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.

The behaviour of the adiabatic logic in the near threshold regime has been analysed in depth in this study. Near threshold adiabatic logic (NTAL) style can perform efficiently using a single sinusoidal power supply which reduces the clock tree management and enhances the energy saving capability. Power dissipation, voltage swing, effect of load, temperature, frequency etc. of NTAL circuits have been detailed here. Extensive CADENCE simulations have been done in 22 nm technology node to verify the efficacy of the proposed model. A power clock has been generated based on a switched capacitor regulator to drive the complex NTAL circuits. Analytical and simulated data match with high accuracy which validates the proposed adiabatic logic style in the near threshold regime. A significant amount of energy can be saved by the adiabatic logic with or without considering the power dissipation of the clock generator.

In order to overcome the boundary effect and boundary lock problem existing in classical Hewlett-Packard (HP) non-linear model, the authors propose a novel window function for the fractional-order HP non-linear drift model, in which the fractional calculus is utilised to reflect the memory property of the memristor device. The novel window function is general and they can take the previously reported well-known window functions as its special cases by turning parameter a. Compared with the integer-order model, the order and a in the fractional-order case is important parameters to flexibly realise the non-linear dopant drift of memristor model even when a wider amplitude range of the input voltage is applied. Simulation results illustrate that their model is flexible, scalable to guarantee the state variable and the memristor value switched between the low and high levels by choosing suitable parameter and a. A simple practical application also confirms the efficiency of their model to reveal the non-linear dopant kinetics of the memristor device.

A low-power microelectromechanical system-based metal–oxide gas sensor along with integrated signal conditioning unit is presented in this study to detect and quantify the variation of H₂ gas concentrations. The interface circuit controls the sensor operating temperature, measures the H₂ gas concentration, contributes a user-friendly interface and can be used with any suitable sensor network. A PIC16F877A microcontroller has been used for this purpose. The temperature of the sensors was stabilised by controlling the actuating voltage of the microheater. Temperatures of the microheater depend on the output voltage of the digital-to-analogue converter (DAC) and were measured by sampling the heater resistance through the use of a voltage divider and analogue-to-digital converters (ADCs). A microcontroller accordingly adjusts the output of DAC's in order to apply the appropriate steering voltage to the heaters. The method employed to measure the concentration of gases is to sample the voltage drop over the resistances of the sensors by ADCs. Alarming system for safety measure was also implemented in this design. The preventive action was taken by introducing an additional feature of wireless communication by sending short message service via global system for mobile modem to the designated emergency number.

In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half-selected cells. This study presents two schemes, one for single-ended and the other for differential sensing SRAMs, to eliminate the half-selection disturbance. In the first proposed scheme, the content of the desired row of the SRAM array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half-selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half-selection resilient schemes to 8 and 6 T SRAMs. Simulation results show that in the presence of radioactive particles, by applying their write-back scheme to 8 T SRAM and their read-before-write scheme to the conventional 6 T SRAM, the failure rate is reduced from an average of 56 and 20%, respectively, to 0. The proposed schemes do not degrade write-ability of the SRAM cells, and are bit-addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.

The authors present two new metal oxide semiconductor field effect transistor (MOSFET)-only second-order voltage and transadmittance-mode band-pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low-power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage-mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth-order voltage and transadmittance-mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid-out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth-order voltage and transadmittance-mode band-pass filter is 1100 μm² and the power consumption is about 436 µW.

An approach of tuning first-order filters is proposed in this study. The proposed approach is based on employing feedback in first-order filter circuits, wherein a scaled output is combined with the input signal, so as to facilitate easy tuning of filter parameters. Various options of tuning the filter parameters are explored by employing feedback from low-pass, high-pass or all-pass outputs. The approach enables easy tuning of filter parameters by varying the gain of an external amplifier, without adjusting the passive elements comprising the filter core. A new current-mode filter circuit is further proposed, which employs a recently introduced active element, namely an extra-X current conveyor. The new approach is used in the designed first-order filter circuit. The new proposed circuit benefits by employing only a grounded capacitor, exhibits low-input and high-output impedances. The approach of tuning filter parameters through external means, without disturbing filter core, and the new proposed circuit are verified through simulations with promising results. As further modification to the proposed approach, the possibility of realising pole–zero symmetry is presented, which makes the new proposed tuning method useful for both existing and future designs.

Emerging technologies in the field of integrated circuits demand wider conversion ratios with a substantial reduction in size and weight. Quadratic buck converter is a popular choice for such an application which is investigated under voltage-mode pulse train control operating in discontinuous conduction mode. The combination of high-power control pulse P _H and low-power control pulse P _L in a control pulse repetition cycle which has a significant effect on the control performance of the system is studied. For a reliable design, a complete assessment of its dynamics under all possible operating conditions is essential for its safe operating horizons. Computer simulations are performed to capture the periodic transformation undergone due to border collision bifurcation. However, the stable periodic operation is examined with the supporting evidence of movement of eigenvalues from 2D discrete-time model and maximal Lyapunov exponent obtained using QR factorisation method for the variation in the input voltage and the load conditions. An experimental setup is also built to verify the system dynamics which are observed in simulations and analytical results.

This study presents a new design of compact transimpedance amplifier (TIA) for optical communication applications. By adopting the regulated common gate (RCG) topology, the proposed amplifier is designed and synthesised based on a third-order elliptic filter approach. Implemented in 0.13 μm complementary metal oxide semiconductor technology, the post layout simulation results provide 50 dB Ω of direct current gain, 15 GHz of bandwidth, as an input referred noise current performance. The proposed RCG TIA occupies a while consuming 5.34 mW under 1.2 V supply voltage, only.

This study presents a low-power 16-bit 1-MS/s successive approximation register analogue-to-digital converter (SAR ADC) for medical instrument applications. A foreground digital-domain calibration method simultaneously correcting mismatch errors in capacitive digital-to-analogue converter (CDAC) and ‘segment error’ of split-CDAC array is proposed. The split-CDAC architecture combines a V _cm-free technique in a floating CDAC scheme. The V _cm-free technique avoids a power hungry V _cm generator, and the floating CDAC scheme allows the conversion of a high-voltage input signal with low supply voltage and without a significant attenuation of the input signal. Moreover, a modified direct-switching SAR logic is adopted to improve the conversion speed. The prototype was fabricated in a 0.18 µm 1P6M Complementary Metal Oxide Semiconductor (CMOS) technology, and achieves 86.16 dB signal-to-noise and distortion ratio and an Figure of Merit (FOM) of 0.41 pJ/conversion-step.