An effective approach for the design of spectrum estimation (SE) in cognitive radio systems using multi-taper method (MTM) and spatiotemporal features is presented in this study, whereas the MTM balances the bias-variance dilemma, the multiple-input–multiple-output (MIMO) and space–time block code (STBC) are customarily aimed to defeat the adverse channel effects and enhance the system capacity and performance. The singular value decomposition is exploited to determine the dominant eigenchannels in MIMO and STBC setups. The maximum-ratio combining, on the other hand, is adopted to produce higher signal-to-noise ratios usually intended for high data rates and reliability levels. The statistical analysis and modelling of the performance metrics associated with the SE based on MTM-STBC and MIMO are approached using the quadratic form approximation. Simulation exercises are employed to compare this different SE, which will be called multitaper spectrum estimation (MTSE), against other typical methods such as the periodogram without tapering options. The results exhibit performance gains due to the merger of MTSE and STBC technologies over MIMO and periodogram SE (PSE) algorithms. Further computational analysis shows that the MTSE–STBC has no extra burdens compared with its PSE counterpart.

This study presents systematic design and detailed circuit analysis of a non-ideal DC–DC pulse width modulation boost converter. An accurate mathematical formula is thrived to evaluate the duty cycle, which enables the converter to neutralise the voltage drop across the parasitic elements. Furthermore, the modified relationships for the design of inductor have been obtained, which satisfy the requirements of stipulated inductor current ripples in the presence of parasitics. Moreover, the mathematical relation is developed to design the output capacitor, which is more accurate than the conventionally derived expression. In addition to this, the output capacitor's equivalent series resistance effect on the output voltage ripples is also investigated. Finally, the experimental and simulation results are used to validate the theoretical analysis.

New realisation scheme of linear voltage-controlled quadrature oscillator (QO) is proposed. The active building block is electronically tunable (ET) differential voltage current conveyor transconductance (g_m ) amplifier configured with current feedback amplifier and multiplication mode current conveyor devices. The designs are essentially tuned-inductor–capacitor oscillator, wherein the electronically variable lossless grounded inductor (L) had been simulated at suitable nodes of the active building block. Subsequently, with slight modification of the block, an ET floating-lossless immittance function generation is presented. Effects of device port mismatch error and parasitic capacitances are analysed. Albeit sensitivity relative to port mismatch error is negligible, the parasitic components tend to limit the higher-usable frequency range; appropriate design equations are derived for a true bilinear admittance function realisation and their applications to filter and sinusoid oscillator design are included. Experimental results on the QO with linear f_o -tuning law are satisfactorily verified up to 8.7 MHz at low total harmonic distortion.

This study presents the analysis and design of a single phase power factor correction (PFC) scheme using a DC–DC single ended primary inductance converter with genetic algorithm (GA)-tuned proportional integral (PI) controllers. A systematic off-line design approach using GA for optimising the parameters of the PI controller is proposed and the performance is compared with the conventional Z–N tuned PI controller. The steady-state and transient responses of the converter subjected to a change in the load, set point and line variations are investigated. The performance analysis of the proposed converter in continuous conduction mode is made for the above-mentioned methods using Matlab/Simulink-based simulation studies and experimental set up. Results reveal that the GA-tuned PI controller yields superior performance to the Z–N tuned PI controller in terms of power factor, percentage total harmonic distortion, regulated output voltage for the variations in line, load and efficient tracking of output voltage for a change in the reference voltage.

An innovative theory on the looped system generating negative time delay is presented. Both the direct and delayed feedback loop topologies of this system essentially consist of an independent-frequency gain and time-delay block. It is shown theoretically that for suitable parameters the system can generate a negative time delay by virtue of a negative group delay (NGD). Analytical expressions reveal that the system presents an unconditional low-pass NGD behaviour. The NGD properties as a function of the system parameters are derived. To demonstrate the feasibility of the developed NGD system concept, frequency- and time-domain analyses are performed with Matlab, resulting in a very good agreement between the simulations and theory. Furthermore, as illustrated by computational results, negative time-delay signal propagation (signal advance) is obtained. The proposed NGD system can potentially be useful for time-delay compensation in engineering systems.

The authors propose an on-chip wear-out monitoring technique, which is based on monitoring the environmental conditions experienced by a digital circuit. The frequency of the T-sensitive ring oscillator (RO) emulates the wear-out stress strength caused by the temperature conditions based on the model of exponential dependence of the stress on the inverse of temperatures. The frequency of the VT-sensitive RO emulates the stress due to time-dependent dielectric breakdown, which is stressed by voltages as well as temperatures. Thus, the accumulated counts driven by the ROs directly indicate the total wear-out stress that the product has experienced so far. The measured results of a test chip fabricated by 28 nm High-k Metal Gate process confirm the expected dependence of T-/VT-sensitive RO frequencies on temperatures and voltages, enabling the emulation of wear-out. The methodology is presented to estimate the stress amount of various wear-out factors having different thermal activation energies. The proposed wear-out stress monitor would make automotive microcontrollers more reliable when they operate at boosted voltages and elevated temperatures to meet performance requirements of cutting-edge applications such as advanced driver assistance systems.

Implementation of basic ternary logic gates is more complex than binary gates in quantum-dot cellular automata (QCA) technology. Several models have been presented for designing ternary logic gates. Most of these models are different solutions and are based on manual calculations. It seems that no simulation tool for designing ternary QCA (tQCA) logic gates has been presented. Unlike previous works, this study is an attempt to introduce an alternative model and the related software for tQCA logic gates. Prominent basic ternary logic gates – such as Min gate, Max gate and inverter – are proposed and simulated in the newly designed TQCAsim software which is an accurate simulation and design tool and is based on the algorithm proposed in this study. Unlike QCA designer software, which has been designed for binary QCA, TQCAsim is designed exclusively for tQCA. Thus, this software can be used to verify and implement the proposed tQCA gates and even earlier designs.

This study proposed an application of symbolic technique on the characterisation of a ring voltage controlled oscillator (VCO) for optimum performance. Here nullor-based symbolic noise modelling and analysis of the CMOS ring VCO is carried out. Circuit equations are processed through modelling of all the metal–oxide–semiconductor field-effect transistors with their nullor equivalent. The closed-form expressions for the total output noise density and phase noise of VCO are obtained. With this technique, the total output noise density and phase noise calculated are compared with the results obtained from the transistor-level simulation. From the comparison, it has been observed that the nullor-based modelling and analysis simplifies the noise expression as well as reduces CPU execution time. The performance enhancement of the VCO is carried out using two different optimisation techniques. These are particle swam optimisation and non-dominated sorting genetic algorithm. The results obtained for the optimised VCO are then tested using SPICE. The SPICE result shows a significant improvement in phase noise, power consumption and tuning range for the optimised VCO.

A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy capacitor switching technique is proposed which consumes no switching energy during the first three comparison steps. Moreover, an energy-efficient split-monotonic technique is utilised for the rest of the operations. Compared with the capacitor switching technique used in the conventional SA-ADC, the proposed scheme not only reduces the switching energy by 99.23% but also it has lowered the total capacitor size by 75%. Furthermore, in order to realise the proposed capacitor switching scheme, a power-efficient logic circuit is designed which reduces the power consumption of the required control logic circuit by reducing the activity of the employed D-type flip-flops. Based on the proposed scheme, a 10 bit 40 kS/s SA-ADC has been designed and simulated in a 0.18 µm complementary metal-oxide semiconductor technology with a supply voltage of 1 V. Post-layout simulation results show that the proposed ADC circuit achieves a signal-to-noise-and-distortion ratio of 60.8 dB at the cost of 270 nW power consumption, resulting in a figure-of-merit of 7.6 fJ/conversion step.

A fully integrated low-power 2.4 GHz ZigBee transceiver with inductor-less radio-frequency front-end in 180 nm complementary metal–oxide–semiconductor is presented. The proposed double push–pull low noise amplifier collaborates with a current-mode down-converter to provide wideband low-noise amplification, as well as the out-of-band blocker resilience. To save power, a sliding frequency synthesiser (FS) with a low-frequency running voltage controlled oscillator is employed to provide the local oscillation for both the receiver and transmitter. Measurement results show that the RX reaches −102 dBm sensitivity and dissipates 11 mA power. The FS achieves −91 dBc/Hz in-band phase noise with only 6.5 mA DC power. The TX features +7.6 dBm maximum output channel power, 4% error vector magnitude at the cost of 19.5 mA power.