In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 ^r . The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 ^r is more specially investigated. RADIX-2 ^r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 ^r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 ^r in high order filters.

An ultra-wideband (UWB) low-noise amplifier (LNA) using a 0.11 µm CMOS technology is proposed. The common-gate (CG) input stage for wideband input impedance matching and the common-source (CS) stage for noise cancelling are applied. In the proposed LNA, the current of the CG input stage can be significantly reduced by applying the g_m -boosting technique using the noise-cancelling CS stage without additional amplifier, and the noise performance can be improved at the same power consumption. For low-power operation, the LNA consumes 2.9 mW and achieves a noise figure (NF) of S ₂₁ between 16.5 and 17.6 dB at S ₁₁, lower than −12.4 and 3.6–3.7 dB at frequencies of 3–10 GHz. In low-noise operation, the LNA consumes 8.3 mW, achieving S ₁₁ of less than −10.7 dB, S ₂₁ of 17.5–18.7 dB, and NF of 2.4–2.9 dB.

A low-jitter delay-locked loop (DLL) for high-resolution time-to-digital converter (TDC) is proposed in this study. The generated high accurate and low-jitter outputs with uniformly distributed multiphase clocks directly from the voltage-controlled delay line (VCDL) in DLL are applied to two-segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal–oxide–semiconductor process, the measurement results show that DLL's frequency locking range is 60–240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak-to-peak. By clock period counting and eight-phase discrimination, the resolution of <1 ns and maximum range of around 1 μs as well as the differential non-linearity <0.68 LSB and the integration non-linearity within −0.97 to 1.24 LSB are obtained for two-segment TDC.

In this study, the authors focus on the problem of model order reduction (MOR) suitable for continuous linear time-invariant (LTI) systems. Specifically, for single-input single-output (SISO) LTI systems, a couple of MOR algorithms via the cross Gramian are presented. The authors first give a cross Gramian-based optimal MOR iterative algorithm to reduce the SISO system. Further, the authors explore the optimisation problem on the Stiefel manifold. Based on the geometric notions on this manifold, a conjugate gradient iterative algorithm (CGIAHM) is proposed. The conjugate gradient direction used to search for the minimiser is derived by applying the notion of vector transport. It is worth mentioning that the conjugate gradient used in the CGIAHM algorithm is a decent direction for the cost function due to the ingenious construction of this algorithm. In addition, the authors’ algorithms are extended to solve the optimal MOR problem for general LTI systems. Finally, two numerical examples demonstrate the effectiveness of their algorithms.

In this study, the authors propose a novel structure of high-electron mobility transistor (HEMT) with significantly improved performance. The novelty of the proposed HEMT is the realisation of two parallel induced electron layers under the source and drain electrode, one in the form of two-dimensional (2D) electron gas (2DEG) and the other in the form of charge plasma electron gas (CPEG). The proposed device is a hetrostructure GaN/AlGaN device, therefore, a 2DEG gets created. However, two metal electrodes at the source and drain terminals are used in the proposed device, which induce CPEG in an undoped AlGaN film under the source and drain electrode. Therefore, the proposed HEMT device is hybrid and has a combination of CPEG and the 2DEG. A two-dimensional (2D) calibrated simulation study of the proposed device has revealed that its hybrid nature has improved its performance significantly in comparison to the conventional HEMT device having 2DEG only. It has been observed that the ON current has enhanced by 115%, transconductance (g _m) by 168%, cutoff frequency (f _T) by 71% and maximum oscillation frequency (f _max) by 65% in comparison to the conventional HEMT.

Series-connected rectenna associations are proposed to improve the harvesting performance of conventional rectenna circuits by recovering power from different directions. With an available input power of −20 dBm, post-layout simulations evaluated the total output power of four series-connected rectennas designed in Complementary Metal Oxide Semiconductor Fully Depleted Silicon On Insulator (CMOS FD-SOI) 28 nm technology, to 14 µW at maximum power point (MPP), while the post-layout simulation of a single rectenna yields 5 µW at the same input power level. However, the rectenna association performance may be significantly degraded when dealing with different input power levels among rectennas. Therefore, a passive bypass circuit has been added at the output of the series association to short-circuit the weakest rectenna. The proposed design is cost-effective since there is a negligible silicon penalty and no additional power losses. In the designed four series-connected rectenna association, the total output power is 7 µW at MPP with the bypass circuit when the strongest and the weakest rectennas receive −20 and −35 dBm, respectively. Also, thanks to the bypass circuit, the efficiency of the rectenna association and the ratio of maximum achieved power are improved by, respectively, 10 and 20%.

In this study, an improvement for two-step write scheme to reduce the resistance change in complementary resistive switch array is proposed. The authors change the amplitudes of write voltages and improve the scheme to three-step write. The disadvantages of the previous two-step write scheme are analysed. Compared with the traditional write scheme, the improved scheme can reduce resistance change about 68%, which does not need any other devices. The average power consumption for this write operation is lower. Through simulation, the feasibilities of the improved two-step write scheme are demonstrated.

A novel scheme to design the hardware for error compensation function which self-compensates the truncation error of fixed width multiplier is presented. The proposed method statistically correlates the compensating carries in the truncated part with the carries generated at the truncation boundary in the non-truncated part. The method also utilises the selective dominant carry compensation for controlling the magnitude of error and hardware complexity. The proposed scheme of error compensation in truncated multiplier is investigated for random inputs, Fast Fourier Transform (FFT) application and Finite impulse response (FIR) application. This proposed scheme shows improvement in the major performance parameters such as mean absolute error, mean-square error, maximum error, standard deviation and variance when compared with previously reported schemes. The scheme noticeably decreases the probability of maximum error to 0.22, 0.11 and 0.2 for input scenarios of random, FFT and FIR applications, respectively, which is minimum in comparison to all existing architectures. The scheme is also investigated for the new proposed figure of merit, i.e. energy error product for the truncated multiplier, to select a balanced error and energy optimised truncated multiplier for specific applications.

This study focuses on the application of a direct interface circuit (DIC) with a microcontroller for the measurement of responses from an array of metal oxide semiconductor (MOS) gas sensors and evaluation of its performance. The authors estimate the uncertainty caused by a sensor circuit and DIC parameters in the measurement of output responses from a MOS gas sensor array. In deriving such a setting, an uncertainty principle is utilised to estimate the ranges of the uncertainty of each parameter causing a deviation in measurement from the true value. The authors explore the extent of uncertainty contributed by both the sensor parameters as well as the DIC parameters of the e-nose system. An experimental investigation demonstrates that the DIC-interfaced MOS gas sensor-based e-nose incorporates various sources of uncertainty.

A new complementary metal–oxide–semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages. The QFG multiple-input metal–oxide–semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 µW. The FDDTA was designed in Cadence platform using 0.18 µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.

In this study, a traditional voltage-mode oscillator consisting of a high-Q band-pass filter and a voltage amplifier is transformed into a current-mode oscillator employing a trans-conductance amplifier. Furthermore, a current-mode quadrature oscillator with a high-Q band-pass filter and second generation current-controlled conveyors (CCCIIs) is presented. Since the loop of the oscillator has rich selectivity, the oscillator produces less distortion. Also, the 3 dB bandwidth, oscillation criterion, and oscillation frequency of the oscillator could independently, linearly, and electronically be tuned by the aid of adjusting bias currents of the CCCIIs. Finally, the validity of the designed circuit is verified by means of the computer simulation and the non-ideal analysis is performed to explain the results of the simulation. The results show that the designed circuit is workable.

Miniaturised transceivers are essential in multiband wireless communication systems for higher data rates and low power consumption. Microelectromechanical system (MEMS) resonator filters are actively considered for deployment in transceivers for radio frequency and intermediate frequency (IF) signal filter and oscillator applications. In this study, the authors propose dual frequency capacitive transduced MEMS resonator with two-port electrical configuration. Clamped–clamped beam resonator was selected to serve as a basic resonant tank for the filter concept validation. Five design strategies low loss structural material, array design, mixed electrical and mechanical coupling scheme, sub-micro meter transduction gap and large transduction area were explored. With these strategies, the device achieves dual band filter characteristics, narrow pass band, desired bandwidth, low insertion loss and better stop band rejection. Dual frequency response of the proposed resonator is demonstrated at centre frequencies 400 kHz and 2.57 MHz with a narrow pass band of 3 and 20 kHz, respectively. Low insertion loss of 19.8 and 25.6 dB for frequencies centred at 400 kHz and 2.57 MHz, respectively and stop band rejection >35 dB was achieved. The proposed MEMS resonator may be incorporated in the implementation of dual band pass filter for IF signal filter and dual frequency oscillator applications.

A novel write bitline (BL) charge sharing write driver (CSWD) and a half- read BL (RBL) pre-charge scheme is presented for a single-ended 8T static random access memory (SRAM). Before write enable (WE) signal assertion, CSWD equalises the write BLs by allowing their charge sharing. Both write BLs are equalised at the middle value of supply voltage using leakage current compensation block. Afterwards, as WE signal is asserted, CSWD produces the rail-to-rail levels at write BL pair. Charging of a BL from half- to essentially reduces the write dynamic power dissipation by 50%. Half- pre-charging is used for RBL to achieve low-power read operation. Read port is powered by virtual ground rail to improve the RBL leakages. The authors compare the proposed 8T design (P8T) with conventional 6T (C6T) and 8T (C8T) designs in a 45 nm technology node. Write power dissipation is reduced by 42% and dynamic read power is reduced by more than 39%. Overall leakages are reduced by more than 18% compared with C6T and ratio of the RBL is improved by more than two orders of magnitude compared with conventional 8T (C8T).

This study presents a spread spectrum clock generator (SSCG) circuit for high-speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage-controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum-spreading profile. The control unit consists of an analogue charge pump-based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high-speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm² active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non-spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works.

An automatic detection system for distinguishing healthy, ictal, and inter-ictal EEG signals plays an important role in medical practice. This paper presents a very large scale integration (VLSI) architecture of three-class classification for epilepsy and seizure detection. In order to find out the most efficient three-class classification scheme for hardware implementation, several multiclass non-linear support vector machine (NLSVM) classifiers are compared and validated using software implementation. Finally, the one-against-one (OAO) multiclass NLSVM is selected due to its highest accuracy. The designed system consists of a discrete wavelet transform (DWT)-based feature extraction module, a modified sequential minimal optimization (MSMO) training module, and an OAO multiclass classification module. A lifting structure of Daubechies order 4 wavelet is introduced in three-level DWT to save circuit area and speed up the computational time. The MSMO is used for on-chip training. The circuit of the largest absolute value decision is designed to avoid the unclassifiable problem in the OAO multiclass classification. The designed system is implemented on a field-programmable gate array (FPGA) platform and evaluated using the publicly available epilepsy dataset. The experimental results demonstrate that the designed system achieves high accuracy with low-dimensional feature vectors.

As process monitors have become vital components in modern very-large-scale integration (VSLI) designs, performance targets often determine the physical implementation of such monitors. However, as various process and environmental parameters collectively affect circuit behaviour, the design of process monitors can be difficult. In addition, process parameters from device-level models may not provide sufficient resolution in circuit-level performance. Therefore, the authors propose an intelligent novel flow for selecting dominant process parameters for evaluating performance targets such as timing and leakage. The proposed flow is applied to ISCAS'85, ISCAS'89, and IWLS'05 benchmark circuits and selects the dominant parameters in 32 and 45 nm complementary metal-oxide-semiconductor (CMOS) technologies. Through this flow, the authors identify the supply voltage, temperature, gate-oxide thickness, and effective gate length as the four dominant factors for timing and leakage. Experimental results show that the suggested process parameters achieve high evaluation accuracy (<3% errors in timing and <1% errors in leakage on average) in the benchmark circuits. Therefore, the proposed flow can select dominant parameters for performance targets, and the four determined factors can be used to accurately evaluate timing and leakage in 32 and 45 nm CMOS technologies.

A reusable comparator stage-based asynchronous binary-search Successive Approximation Register (SAR) analogue-to-digital converter (ADC) with a smart reference range prediction network is presented in this brief. The proposed architecture has an advantageous merit of using only N comparators in comparison with original binary-search ADC and flash ADC. The design uses selection logic which selects and activates the comparator one at a time, and a smart switching network which allocates reference voltage to selected comparators in the successive comparison process. It claims for equipoise with power and operating speed when compared with flash ADC and SAR ADC. The post-layout simulated performance of 6 bit conversion using only six comparators on United Microelectronics Corporation (UMC)-180 nm achieves 41 dB spurious-free dynamic range and 36.02 dB signal-to-noise distortion ratio with a maximum sampling speed of 330 MS/s consuming 0.64 mW power when operated at 1.8 V supply, corresponding figure-of-merit 36.47 fJ/conversion step.