It is challenging to develop a physically based compact model for an organic thin-film transistor (OTFT). Moreover, there is still a lack of a universal model that would cover the huge variety of materials and device structures available for state-of-the-art OTFTs. Different models of charge transport phenomenon in organic semiconductors are briefly explained, since such phenomenon constitutes the basis of a physically based compact model of an OTFT. An introduction to the basic principles dictated on compact models suitable for Computer Aided Design (CAD) simulators is stated. Six reported models are presented and analysed with an emphasis on their primary assumptions and applicability aspects. Furthermore, the selected compact models are compared with experimental results provided by a fabricated OTFT. Finally, the authors conclude recommendations for advancing OTFT compact modelling in order to reach a more enhanced model that could characterise most recently reported OTFTs.

This study presents the analysis of statistical parameters of the output quantisation noise amplitude distribution in the analogue-to-digital converter (ADC) with oversampling and decimation. Hypothesis was tested that quantisation noise amplitudes on the output of the system have a Gaussian distribution. To test this hypothesis, Chi-squared statistical test was performed with parameter estimation based on grouped data. Simulation models were made for two types of ADCs: classical b-bit and sigma–delta. Various realisations of decimation filters were used as well as various values of the decimation factor. Based on the number of cases in which the hypothesis was rejected, the significance of the test was determined, i.e. the deviation from the ideal Gaussian distribution was quantified. Results of this research can prove to be useful in system design process, where accurate knowledge of the quantisation noise statistical model parameters is required. This study presents general procedure for analysing the amplitude distribution of the quantisation noise, which can easily be implemented on other modified models of the ADC with oversampling.

Filterbank multicarrier has been proposed as an alternative to rthogonal frequency division multiplexing (OFDM). A uniform Discrete Fourier Transform (DFT) transmultiplexer cannot have maximum packing efficiency while using slowly decaying pulses. Maximally decimated filterbanks and transmultiplexers can be used interchangeably. Designing a filterbank with large number of independent filters can be a tedious job. So, wavelet packets have been tried as a basis for multicarrier modulation. However, real wavelet packets have energy on both sides of the spectrum, making the use of a single tap equalisation and usage of water-filling algorithm difficult. The authors propose a cascade of filterbanks which produce nearly analytic waveforms. They also design a class of 3-band filterbanks whose high-pass filters are structurally complex conjugate pairs, which reduce the complexity of the design. A 5-band filterbank is also designed with similar properties and a hybrid cascade of filterbanks is also investigated. The performance of the cascade and hybrid cascade through a wireless channel is compared with OFDM without cyclic prefix and Daubechies wavelet packets. In highly frequency selective channels, the proposed cascaded filterbank design outperforms OFDM without cyclic prefix and Daubechies wavelet packets in terms of error rate.

A new generalised Lorenz three-dimensional integer-order non-linear system is constructed, and integer-order derivatives are simply replaced by fractional-order ones. Transfer functions in Laplace domain have been calculated and compared for a set of fractional orders q _i in (0, 1) with decrement of 0.025 for the maximum error Y = 1 dB/2 dB/3 dB. A novel basic fractional-order unit circuit named ‘Assemble Type’ is designed consulting to the four existing unit circuits, which are ‘Chain Type’, ‘Tree Type’, ‘Mixed Type’ and ‘New Type’. Meanwhile, it is compared with the four existing unit circuits in circuit theory and applications. The novel fractional-order unit circuit is applied to the circuit simulation of Lorenz system combined with the other four unit circuits, and circuit simulation shows that they have very resemble chaotic behaviours, actually, the scheme can be applied in any tiny values of q _i , which shows that the fractional-order system has better effectiveness, flexibility and universality. Finally, using stability analytical method based on two stability theorems and necessary conditions to exhibit validity and feasibility of this novel-type design.

A novel resistance-to-digital converter (RDC), based on the integrating type analogue-to-digital converter principle, is presented in this study. The conversion time of the proposed scheme is not a function of the current value of the parameter being measured. Thus, by suitably setting this parameter, the converter can be made to reject the effects of interference at a particular frequency, such as, that due to power-line at 50/60 Hz. Error analysis was conducted to ascertain the effects of non-idealities of various components of the circuit, on its output. Simulation studies were carried out in LTSPICE to verify the linearity and the interference rejection capability of the converter. Further, a prototype RDC was developed in the laboratory and tested to confirm the results of the simulation.

This study presents the new locking range enhancement technique in divide-by-two injection locked frequency divider using a phase shifter circuit. The proposed divide-by-two phase shifter injection locking frequency divider (ILFD) is based on complementary metal–oxide–semiconductor (CMOS) cross-coupled oscillator with dual-resonance fourth-order LC-tank that is designed and simulated in 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology. Using a phase shifter branch, an extra current with a new phase angle towards oscillator current will inject into the LC tank and moves the locking angle to a new and wider angle that leads to a wide locking range. In an analysis, the effect of the phase shifter circuit on the proposed ILFD has been explained. Simulation results show that at a supply voltage of 0.95 V, the phase shift ILFD consumes 7.32 mW power and at the incident signal power of 0 dBm the locking range is 5.25 GHz, from 4.3 to 9.55 GHz and the relative locking range is 75.81%.

This study presents a methodology for recursive implementation of linear-phase finite impulse response (FIR) filters in fixed-point hardware platforms. The work uses a modified version of the switching and reset method to efficiently implement recursive linear-phase exponential filters. An error analysis is presented that defines the upper error bounds resulting from the switching and reset implementation of the exponential filters in fixed-point hardware. The exponential filters are then used as basis functions to synthesise other filters of interest. Gaussian filters are used as an example. The suggested recursive implementation delivers an accurate approximation of the Gaussian function. Unlike traditional techniques for implementing FIR filters, the hardware size of this recursive technique is O(1). In other words, increasing the order of a filter does not proportionally increase its hardware size. The results show that when implementing Gaussian filters on FPGAs, doubling the size of the filter, only increased the hardware size by an average of 6.12%.

Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field-effect transistors (CNFETs) can easily be utilised for multiple-V_t circuit designs. In this study, a novel energy-efficient method for designing one-digit adder is proposed. The suggested design employ ternary multiplexers to select and of input trits for the output node values. This study describes the novel ternary multiplexer, and cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state-of-the-art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

Electroencephalography (EEG) is an effective tool to non-invasively capture brain responses. Traditional EEG analogue front end (AFE) requires a driven right leg (DRL) circuit that restricts the number of channels of the device. The authors are proposing a new ‘DRL-less’ AFE design, and have developed a wearable EEG device (NeuroMonitor), which is small, low-power, wireless, and battery operated. The EEG device with two independent channels was fabricated on an 11.35 cm² PCB that contained a system-on-a-chip microcontroller, a low-noise instrument amplifier, a low-power Bluetooth module, a microSD, a microUSB, and a LiPo battery. The DRL circuit was eliminated by utilising the high CMRR instrument amplifier with differential inputs, and followed by a modified high-Q active Twin-T notch filter ((f_c ^Notch = 60 Hz,  − 38 dB). The signal was conditioned with a band-pass filter composed of a two-stage 2nd-order Chebyshev-I Sallen-Key low-pass filter cascaded with a passive 2nd-order low-pass filter (f_c ^LP = 125 Hz) and a 1st-order passive high-pass filter (f_c ^HP = 0.5 Hz). Finally, the signal was amplified to achieve an overall gain of 55.84 dB, and digitised with a 16-bit delta-sigma ADC (256 sps). The prototype weighs 41.8 gm, and has been validated against a research-grade EEG system (Neuroscan).

This paper presents an adaptive g _m3 cancellation for linearisation of operational transconductance amplifier (OTA) and its application to design of a wide tunable Gm-C filter. g _m3 cancellation through paralleling triode- and subthreshold-mode transconductors makes good linearisation, but only in a limited range of tuning voltage. An auxiliary circuit is employed to adaptively change the operating point of subthreshold-mode transconductor such that to keep linearisation throughout the tuning range. By this way, the linearity of OTA is significantly improved in overall transconductance tuning range from 18 to 289 μA/V. While by applying 0.6 Vpp input voltage at 1 MHz the total harmonic distortion (THD) of conventional OTA lies between −75.1 and −44.4 dB, it reduces to lie between −83.3 and −57.4 dB in the proposed OTA. Using the proposed OTA, a third-order low-pass Gm-C filter is designed in 0.18 μm CMOS technology. The cutoff frequency of filter is tunable from 1.73 to 27.25 MHz, thus, can be applicable to support WCDMA, WLAN (IEEE 802.11a/b/g/n) and WiMAX standards in multi-mode direct conversion receivers. The third-order intercept point of filter is between 7.1 and 13.7 dBm in different tuning conditions.

This study presents a COordinate rotation DIgital computer (CORDIC)-based novel architecture combining the sliding discrete Fourier transform (DFT) with Hann windowing to reduce the leakage effect of the DFT spectrum. The proposed architecture also presents a refreshing approach to minimise error due to the finite word-length in the output windowed spectrum compared with the existing method. The architecture can also be extended for other high order generalised cosine windows such as Blackman, Blackman–Harris, and flat-top. The post-route results on the Virtex-6 FPGA as well as the physical ASIC post-layout results are also presented for the proposed architecture.

This study presents two simple and efficient linearisation circuits for giant magneto-resistance (GMR)-based magnetic field sensors. GMR sensors are commonly available in wheatstone-bridge form, comprising two active GMR and two passive GMR elements. The output of such a sensor possesses a non-linear dependence on the input magnetic field. The proposed linearisation circuits operate on the output of a GMR sensor and provide a linear output with respect to the magnetic field. The first GMR linearisation circuit (GLC₁) is based on an enhanced feedback compensation approach, while the second (GLC₂) scheme uses a constant current technique. The methodologies of the schemes are described using mathematical derivations. Detailed analyses of the schemes are carried out to bring out the effects of circuit and sensor non-idealities on circuit performance. Further, the circuits were implemented on printed circuit boards and tested. Test results showed the capability of GLC₁ and GLC₂ to produce linear transfer characteristics. A prototype GMR sensor unit was then fabricated and tested with the developed circuits. Output non-linearity obtained during the experimentation was around 0.7%. Analyses of the results proved the superior performance of GLC₁ and GLC₂ over the existing schemes.

This paper presents circuit design and simulations of a high gain organic Op-Amp, for use in quantification of real cholesterol, in the range of 1–9 mM. A 7-stage inverter chain is added onto the design so as to enhance the amplifier gain. The circuit adapts p-channel transistors only (PMOS) design architecture with saturated loads, simulated on a conventional platform, using appropriate OTFT model and associated parameters. The effect of variation in threshold voltage on circuit operation is also examined. For a supply voltage of ±15 V, the DC output voltage is found to be within an acceptable range of −1 V to −12.5 V, with a highest open loop gain of 83 dB. The closed loop gain is also in agreement with theoretical values, in the range of 1.5 dB to 39 dB, with corresponding bandwidths of 770 Hz to 275 Hz respectively. The latter gain of 39 dB and/or gain-bandwidth product of 10.63 kHz is currently the highest reported in the literature, for this lower supply voltage. The amplifier offers adequate quantification factor, with linear sensitivity of −0.7 V/mM. This paper is the first to adapt organic circuit designs in quantification of cholesterol, with promising outputs, for implementation in low-cost sensor systems.

Regular structures, like datapath, are important components of integrated circuits. Datapath logic is usually placed with high regularity and compactness for higher performance by using manual placement. The authors propose effective datapath regularity extraction and placement (DREP) techniques which simultaneously place datapath logic and random logic. This method detects datapath logic and effectively formats regular datapath structures while optimizing the order of functional stages and placement of datapath blocks. Moreover, the datapath structures are further optimized by using bit-slice order adjustment and partitioning techniques during global placement. Partitioning of a big datapath macro greatly increases the placement flexibility, since partitioned sub-blocks of the datapath macro can be optimally placed with other blocks. A new effective method is also suggested to decide the block to be partitioned and the granularity of partitioning. Similar to the manual placement results, the datapath logic is regularly placed and the datapath cells are aligned well, vertically or horizontally by the DREP techniques. When compared with the state-of-the-art works, the experimental results show that the new techniques produce significantly better results than other methods in terms of half perimeter wire length, Steiner wire length, and routability, measured from the detail routing results.