In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

As heterogeneity in desktop processor chips was recently promised by the major manufactures, the importance of these new architecture paradigms strongly grows. Especially if programmable CPUs are combined with reconfigurable logic like it has been done in the embedded domain, the complexity to design an energy efficient and powerful system increases. Therefore, heterogeneous system platforms have to be focused even stronger in research and education. Because the design and programming of these architectures is much more complex than using standard processor solutions, it is essential to provide thorough education programs for students. Only then will the engineers of tomorrow be able to deal with the future challenges. As a consequence, the authors restructured their curriculum to especially deal with the upcoming needs. Three courses were oriented towards the common goal of developing a real-world smart camera solution utilising heterogeneous architectures. The new combination provides various synergistic benefits and evaluation results confirm, that the overall orientation of the courses is a step in the right direction. As the basic components are already available at many other universities, their example can encourage to launch similar programmes elsewhere.

Radio-frequency integrated circuits (RFICs) design and fabrication require sets of skills that are professionally earned through years of hands-on experiences in a developed industrial environment such as fabless design houses. Difficult design specifications, dynamic working environment, and tight deadlines in ruthless time cycles of design to mass production are all, but few examples that academia often fails to train young engineers to face. In general, no skill-based education can be easily found for fresh graduates interested in a career in IC design. As part of an industry-oriented graduate course in RFIC, students were introduced into industry design flow through lectures and major project assignments. The latter were selected to form an integrated design flow that ultimately leads to the design of a full RFIC. Students were offered to select design blocks as projects and were given specifications to meet, extracted from a transceiver architecture study. The outcome of the work showed an interesting trend of students starting their design in individual efforts, but later clustering together in team effort to match their designs together and to finish their tasks at the fictitious tape-out deadline.

This study describes the design and evaluation of a secure chip design module for graduate students and junior engineers with electronics and computer engineering. This course has two broad goals, the first is to teach students how design complex systems on chips using industry standard tools and the second is to educate them on emerging hardware security threats and countermeasures. There are a number of strategies currently been employed to handle the rising complexity of chip design, namely reuse, abstraction and automation. The authors aim to show how to employ these approaches to produce working systems within a time-constrained environment similar to that of IC design companies. One of the unique features of this module is its approach of treating hardware security as an integral part of the chip design process and as one of the design metrics which can be evaluated and optimised, this allows students to better understand the root causes of this issue and to think more constructively about potential countermeasures. The course is designed based on the principles of constructive alignment method and Kolb learning cycle. Detailed syllabus and assessment exercises are included. Feedback results from students' surveys indicate that the module has been positively received.

To validate the concept of an electronic system before thinking of commercial uses, a prototype needs to be developed first. However, technical knowledge in electronics and computer science (CS) is required. Due to the importance of these fields in the world of today, where almost everything is regulated by technology, several initiatives emerged to provide the general public with these knowledge. In this context, there is a focus on the education field where several efforts have been made to lower the entry level to electronics and CS fields, enabling even kids to learn the basic concepts at an early age and have the possibility to concretise their ideas and develop their own prototype. The study presents a solution to facilitate the task of programming electronic gadgets using graphical programming. The authors consider as case study an electronic system built around the IOIO board. The graphical programming interface was created using App Inventor, a web platform for creating android apps. Using the proposed system, several basic and complex gadgets were easily created by young school children with minimal skills in hardware assembly and software programming.

Since 2001, the departments of Electrical and Electronics and Information and Communication Electronics Engineering of Faculty of Engineering, the University of Tokyo (UTokyo) have jointly given a lecture on autonomous electronic information devices for undergraduate students. According to the on-line questionnaire, 80% of students in 2010–2012 replied that the lecture was useful for their future career. The task given to students was to design and realise an autonomous electronic information devices (so-called ‘the IoT-gadgets’) by themselves, and conduct a live demonstration in front of their colleagues. The device must have an ‘input’, ‘output’, and some ‘information processing’. Being aware of the speed of technology evolution as well as the short hours of the lecture, the professor tried not to give direct answers to students’ questions on how-to instantly build and program an information device. Instead, the students were told to beware of their ‘methods’. This refers to the deductive thinking introduced by René Descartes, and in the lecture's context how students should behave in order to realise the device. In this study, the backgrounds of various associated topics are discussed, such as the UTokyo's educational system, the world's rapid prototyping movement, open hardware, course design, students’ reactions, and future directions.

The study discusses the design principles of instructional laboratory equipment applied for practical investigations of electric drive control. The laboratory workstations comprise of two-motor hardware systems where each motor is controlled by a real-time DSP board. A control structure under test is assembled at the software level using a number of control elements, which is then compiled into a control algorithm for the microcontroller. In order to provide safe test execution, the control algorithm operates under the supervision of a real-time core software ensuring protection of the motors and the power converters. Due to the improvement in the reliability of hardware operation, the rated power of the motors and converters is increased to >1 kW to provide a proper characterisation of electric drives similar to industrial installations. The study also describes the laboratory hardware and software details using an example of the control system for an induction motor based on flux-vector control strategy. The example demonstrates configuring the control systems, compiling it into the execution code, the test procedure and result analysis.

Eddy current testing (ECT) is one of the non-destructive evaluation techniques widely used, especially in oil and gas industries. It characterized noisy data to the less-than-perfect detection and as an indication of serious false alarm problem. However, not many researchers have described in detail the intelligent ECT crack detection system. This paper introduces a review of ECT technique and factors that affect the signal fundamental according to the hardware and software development. First, describe the magnetic excitation resources including the sinusoidal and pulse exciting signal. Second, outlines explanation about the ECT probe. The explanations are more about the probes development for air core probe and giant magnetoresistance probe. Third, there is discussion on ECT circuit that used including ECT system, ECT rotating magnetic field and application measurement for optimal control parameters. The defect in characterizations and measurement are discussed on the fourth part of this paper. The fourth part discusses the ECT lift-off compensation including the lift-off and application of intelligent technique in ECT. The limitations of lift-off for coil probe and compensation techniques also discussed in this part. Finally, a comprehensive review of previous studies on the application of intelligent ECT crack detection in nondestructive ECT is presented.

Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.

In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF-state current and subthreshold swing (SS) are significantly high for the double gate Ge source/drain symmetric p–n–p tunnel field effect transistor (TFET) with a silicon channel without n⁺ pockets at the source- and drain-channel interfaces. They further establish that using pockets at the source- and drain-channel interface, the Ge source/drain symmetric p–n–p TFET exhibits a 130 times improvement in I _ON/I _OFF ratio and a 26% reduction in SS due to the two orders of magnitude reduction in its OFF-state current when compared with the one without the n⁺ pockets. The results also indicate that the Ge source/drain symmetric p–n–p TFET suffers from a low output conductance at low drain voltages. Since the proposed device exhibits bidirectional current flow, it can be easily integrated with the conventional complementary metal-oxide semiconductor technology.

DC–DC converters have led rapid development in electrical engineering owing to their virtuous assets in industrial field. Wide utilisation of power equipment in various arenas has led to stringent electromagnetic interference (EMI) and this issue is more common in DC–DC converters. In this study, a method has been put forward to mitigate EMI in peak current mode controlled elementary DC–DC converters by introducing quasi resonant (QR) intrusion. Results are demonstrated with time domain simulations which are attained from an exact non-linear time varying model developed without any quasi-static approximation. Stability analysis is performed using monodromy matrix based on Filippov's method. Experimental findings are found to agree well with simulation and arithmetical results, thereby confirming the qualitative and quantitative behaviour of the system for different parametric deviations. In addition, it is observed that the QR intrusion improves the stable operating regime and makes the converter electromagnetically compatible by mitigating the spurious signals.

In High Efficiency Video Coding (HEVC) standard, higher video resolutions employ larger integer Discrete Cosine Transform (DCT)/inverse DCT (IDCT) block sizes. In this study, the authors propose two high-throughput unified DCT/IDCT architectures. The proposed architectures can process variable DCT/IDCT block sizes according to the HEVC standard. The proposed architectures were prototyped on TSMC 65 nm CMOS technology. The prototyping results show that the two unified architectures have throughput of 15.24 and 16.03 Gsps, respectively, and they can encode video sequences with resolutions up to 8 K at 120 fps and decode the same resolution at 240 fps using only one circuit for both DCT and IDCT.

Lithium batteries must be connected in series to achieve large capacity and high-power output. Battery management system (BMS), which is designed to protect battery pack from damage and increase battery life, is important in electrical power system. The present equalisation techniques have many disadvantages: The passive balancing wastes energy and generates heat, while active balancing is complex. This study proposes an intelligent BMS with dynamic equalisation (DBMS) which contains active and passive balancing circuit independently per cell. Experimental results indicate that DBMS can reduce the inconsistency among cells. Moreover, the DBMS can assist battery stack to store and release more energy. Besides, the battery stack with DBMS gives an energy efficiency of 96.5% which is 7.7% higher than that without balancing. In addition, the battery stack with DBMS can reduce the maximum state of charge difference of cells from 10.415% to 4.51% after three charge–discharge cycles. What is more, the DBMS is simple and can decrease the auxiliary power level and the system heat. Such a DBMS will help us to provide a high-performance battery pack.

The single-electron transistor (SET) is considered as a promising alternative to CMOS devices and integrated circuits due to its ultra-low-power consumption. The authors propose an automatic methodology by utilising SET-based multiway decision graph (MDG) for implementing SET architecture. MDG provides a powerful means of abstraction and can be used to manipulate a certain type of first-order logic formula called directed formula (DF). An automatic tool has been developed that is capable of transferring the SET array into MDG DF to generate all paths of all possible reachable states, drawing an abstract diamond-shaped network for the SET array, producing a reduced DF generated by the MDG tool and converting the reduced DF into a conjunctive normal form formula. Then, the authors use the satisfiability approach as a verification engine to verify the correctness of these conversions. The method is tested and verified using MCNC benchmarks. The results outperform approaches based on binary decision diagrams in terms of verification time, number of clauses and variables.

A new technique to characterise the behavioral response of multistage RF power amplifier (PA) is presented. A simplified design methodology of closed loop PA with DC current sensing of multistage PA (cascaded) and voltage shaping algorithm is introduced in this study. An accurate characterisation of transient behavioral which includes ramping of RF energy from noise level to steady state level and adjacent channel transient power (ACTP), shows a high degree of correlation with measurement level for wideband RF PA operation (400–520 MHz). A prototype board is fabricated and measurement results demonstrated good correlation with transient behavioral model simulation. On board measurements demonstrated transient timing response of 1 ms while maintaining good ACTP of less than -60 dB over the wide frequency range of 400–520 MHz.