The response of a commercial super-capacitor to an applied periodic current excitation in the form of a triangular waveform is investigated in this study. This waveform has a linear-with-time variation which enables linear charging and discharging of the device. A model consisting of a linear resistance R _s and a constant phase element is used to describe the super-capacitor impedance and expressions for the voltage across the device, the power, and stored energy are derived using concepts from fractional calculus. Experimental results are shown and an application of the study to super-capacitor parameter extraction is described.

This study represents designing and implementation of a low power and high speed 16 order FIR filter. To optimise filter area, delay and power, different multiplication techniques such as Vedic multiplier, add and shift method and Wallace tree (WT) multiplier are used for the multiplication of filter coefficient with filter input. Various adders such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder are analysed for optimum performance study for further use in various multiplication techniques along with barrel shifter. Secondly optimisation of filter area and delay is done by using add and shift method for multiplication, although it increases power dissipation of the filter. To reduce the complexity of filter, coefficients are represented in canonical signed digit representation as it is more efficient than traditional binary representation. The finite impulse-response (FIR) filter is designed in MATLAB using equiripple method and the same filter is synthesised on Xilinx Spartan 3E XC3S500E target field-programmable gate array device using Very High Speed Integrated Circuit Hardware Description Language (VHDL) subsequently the total on-chip power is calculated in Vivado2014.4. The comparison of simulation results of all the filters show that FIR filter with WT multiplier is the best optimised filter.

Wire-crossing plays a pivotal role toward the progress of non-complementary metal–oxide–semiconductor technology. Hefty amount of wire-crossings leads to many complications including cross-talk, colossal power dissipation and high cost function which in turn makes the fabrication difficult. In this regard, this work presents an efficient method for circuit implementation based on majority logic in quantum-dot cellular automata (QCA) with optimum wire-crossing. The authors’ proposed method is able to eliminate wire-crossing by the generation and routing of proper intermediate function in the circuit utilising the orientation of the input variable. An algorithm to minimise the number of wire-crossing is also reported. Experimental results establish the effectiveness of the proposed method in circuit level also. Finally, a concrete framework to design a cost-effective logic circuit in QCA ensuring the least/optimum wire-crossing is established.

Magnetic component tolerances are caused by variations in air-gap and core relative permeability. This study presents the derivation for sensitivity of effective relative permeability to variations in the relative core permeability and relative gap length for magnetic cores with and without fringing effect. The expressions for the fringing factor and effective relative permeability for the magnetic cores have been derived. The effect of air-gap on the core properties, which includes core power loss density, magnetic flux density, and magnetic field intensity is addressed for cores used in low-frequency and high-frequency applications. An example core is selected to support the theoretical predictions. The expressions to determine the inductor tolerances are presented.

In this study, an event-driven detection method based on pseudo-differential self-timed inverter-based incremental sigma-delta analogue-to-digital converter (IDC) is proposed and analysed, which is adapted for sparse signal measurement. A judgment module is implemented to detect whether the input signal of the measurement system is beyond a threshold or not. The input signal will be converted by the IDC only when it is beyond the threshold. A pseudo-differential self-timed inverter-based IDC is also proposed in the event-driven detection technique. The proposed event-driven detection technique is designed and simulated with 1.5-V supply voltage. The IDC achieves 12.8-bit ENOB at 2-KS/s conversion rate and consumes 45 μW. Its figure-of-merit is 3.1 pJ/step and input range is 0–2.4 V. The sparse signal measurement system with the proposed event-driven detection method based on self-timed IDC is implemented. The average power consumption of the system is related to the event ratio. With the event ratios of 10, 20 and 30%, its power consumption will be 30, 34 and 37 μW, respectively. The event-driven detection method improves the power efficiency of the sparse signal measurement system.

A symbolic analysis is presented to study a gain-boosted telescopic operational transconductance amplifier (OTA) with cross-coupled capacitor (positive feedback) across an auxiliary op-amp. The effects of positive feedback capacitor (PFC) on the pole–zero doublet introduced by the auxiliary op-amp are explored using analytical techniques and simulations. A complete transfer function of the OTA with PFC across the auxiliary op-amp is derived and verified through circuit simulations. The results obtained from circuit simulation and modelled transfer function show good agreement with each other. Furthermore, the analytical expressions for the feedback capacitor in terms of pole–zero locations, unity gain bandwidth (UGBW) and phase margin (PM) are presented. It is shown that UGBW, PM and settling behaviour of the OTA can be tuned by the PFC. A systematic design approach to improve the PM and settling behaviour is discussed. On the basis of the theory presented, 17% improvement in 0.01% settling time is demonstrated.

In this work, performance of dielectric inserted side contact multilayer graphene nanoribbon (Di-side-GNR) coupled interconnects using unconditionally stable finite-difference time-domain (USFDTD) technique has been investigated. The model developed for the same, overcomes the limitation of Courant stability criterion prevalent in the conventional finite-difference time-domain (FDTD) technique. The proposed model accurately analyses the crosstalk effect in copper (Cu), side contact multilayer graphene nanoribbon and Di-side-GNR interconnects. It is found that the crosstalk effect is least in Di-side-GNR amongst the three types of interconnect considered in this study. The proposed model and HSPICE simulation results match closely. Further, for transient analysis USFDTD technique based proposed model takes nearly 1.5 times lesser CPU runtime compared to the conventional FDTD technique.

The study presents the algorithm design, non-ideal effect analysis, architectural analysis and design, circuit analysis and design of an iterative frequency calibration system that corrects frequencies consuming very low energy. The method is based on measuring the ‘fraction’ portion when an oscillator frequency (typically of a radio frequency oscillator) is divided by a fixed reference frequency. It then compares the obtained fraction value with the target fraction value (target frequency divided by the same reference) and finally corrects the oscillator frequency so as to converge it to the target. A salient feature of the proposed architecture of the system is the absence of elements in the radio frequency path which is considered to be the main source of power consumption. The system can be used in applications that do not require stringent phase-locking e.g. wireless sensor nodes. Test of the calibration system has been performed in conjunction with a Medical Implant Communication Service (MICS) band (402–405 MHz) oscillator. Successful convergence has been achieved over a wide range of sampler delay variation and oscillator jitter, which are the circuit level non-idealities that arise in the system.

Fin field-effect transistors (FinFETs) are replacing the traditional planar metal–oxide–semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

In the authors’ previous work on the multiplication by a constant, optimisations have been done on the RADIX-2 ^r heuristic based on Radix-2 ^r arithmetic, which is a fully predictable, and a sub-linear-runtime heuristic. This improved version of RADIX-2 ^r is called RADIX-2 ^{r +}. The latter makes the former more competitive in term of average number of additions compared with existing heuristics. In this study, the authors propose a new heuristic for multiplication by a constant, denoted H-RADIX, which combines RADIX-2 ^{r +} with a common sub-pattern (Lefevre's CSP) heuristic. It belongs to the category of common subexpression elimination algorithm. Results of the designed hybrid algorithm (H-RADIX), namely, the average number of additions and the smallest value that requires q adders, are compared with the standard canonical signed digit (CSD) representation, RADIX-2 ^{r +}, and Lefevre's CSP algorithms. The results highlight the efficiency of the designed heuristic, up to N-bits = 64. H-RADIX uses 37.496, 5.015 and 3.082% less additions than CSD, RADIX-2 ^{r +}, and Lefevre's CSP, respectively.

Research of power supplies for megahertz (MHz) class applications such as a semiconductor manufacturing apparatus, induction heater and wireless transfer is carried out. A liner amplifier is generally used for MHz class applications. The loss of the power devices on a liner amplifier is theoretically high. To reduce the loss, the class E and Φ₂ inverters are proposed, and some of the resonant gate drive circuits (GDC) are utilised at those of the gate port. However, the control signal of the GDC becomes complicated due to the additional switches. Moreover, the switches in the GDC perform the hard-switching, and the drive loss can thus be increased. In this study, a multi-resonant gate drive circuit is proposed, and its design method is introduced. It can generate the trapezoidal wave gate-to-source voltage with the simple control signal, and zero voltage switching operation is achieved at the switches of the gate drive circuit. First, its operation is experimentally verified. Secondly, the drive loss is also compared with that of the conventional circuit. Furthermore, its operation with the class E inverter with a cascode GaN high-electron-mobility transistor (HEMT) is confirmed at the switching frequency 13.56 MHz.

Aggressive power cycling of DC–DC converters is becoming important in many applications ranging from sensor interfaces to wireless transceivers, where the system needs to be on for only short time intervals. In this study, a switching DC–DC converter in a discontinuous-conduction mode is proposed. The DC–DC converter is well-suited for light-load applications and features a very short start-up time of 330 ns. This short start-up time makes it suitable for aggressive power cycling, since it can turn on quickly to provide the required voltage for its load. The proposed control loop allows for the short and smooth start-up behaviour of the DC–DC converter to exhibit no overshoot in the transient output voltage. Experimental results in a 65 nm CMOS show that this DC–DC converter has an efficiency of 72–80.3% for input voltages ranging from 2.4 to 3.4 V and output voltages ranging from 1 to 1.2 V. This is achieved when connected to a light load of 100 Ω, and using relatively small inductor and capacitor values of 200 nH and 40 nF, respectively.

Field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiation-induced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.