In this paper, an efficient high-speed architecture of Gaussian normal basis (GNB) multiplierover binary finite field GF(2 ^m ) is presented. The structure is constructed by using some regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. For the powers of 2 exponents, the modules are implemented by some simple cyclic shifts in the normal basis representation. As a result, the multiplier has a simple structure with a low critical path delay. The efficiency of the proposed multiplier is examined in terms of area and time complexity based on its implementation on Virtex-4 field programmable gate array family and also its application specific integrated circuit design in 180 nm complementary metal–oxide–semiconductor technology. Comparison results with other structures of the GNB multiplier verify that the proposed architecture has better performance in terms of speed and hardware utilisation.

Dynamic dataflow allows simultaneous execution of instructions in different iterations of a loop, boosting parallelism exploitation. In this model, operands are tagged with their associated instance number, which is incremented as they go through the loop. Instruction execution is triggered when all input operands with the same tag become available. However, this traditional tagging mechanism often requires the generation of several control instructions to manipulate tags and guarantee the correct match. To address this problem, this work presents three dataflow loop optimisation techniques. The stack-tagged dataflow is a tagging mechanism that uses stacks of tags to reduce control overheads in dataflow. On the other hand, as nested loops may increase the overhead of stack-tag comparison, tag resetting can be used to set the tag to zero whenever it is safe, allowing a one-level reduction at the stack depth. Finally, loop skipping allows to further avoid stack comparison overhead in loops, when the number of iterations can be determined by the compiler. Experimental results show the overhead, drawbacks and benefits for the three optimisations presented. Moreover, the results suggested that a hybrid compiling approach can be used to get the best performance of each technique.

With the increase of research interest on memristors, various single or multiple memristor configurations have been integrated with advanced complementary metal–oxide–semiconducor technology, which promises efficient implementations of synaptic connections in neuromorphic computing systems, or computing elements in signal processing systems. In this study, multiple memristors, both in series and parallel connections, and their characteristics are further studied including the transient behaviours when asynchronous change happens and the composite electric properties in steady state etc. Particularly, the specific conditions to reach steady state and produce composite memristive effects are presented in detail. Furthermore, several synaptic memristor circuits based on series and parallel connections are also discussed.

Among all basic arithmetic operations, the division is the most complex one. On the other hand, working on post-complementary metal–oxide–semiconductor (CMOS) technology attracts attention of many researchers, while the progress of miniaturisation in CMOS technology faced physical limits. Therefore, in this study, the authors propose a non-restoring divider in quantum-dot cellular automata (QCA), as one of the most promising technology. To achieve an efficient divider, they propose a novel 1 bit full-adder and take advantage of improved design of XOR gate. This design has considerable improvements in terms of cell numbers, delay and area, compared with other dividers. The suggested design is simulated in QCADesigner software and acceptable results are achieved.

A real-time thermal imaging based, non-contact respiration rate monitoring method was developed. It measured the respiration related skin surface temperature changes under the tip of the nose. Facial tracking was required as head movements caused the face to appear in different locations in the recorded images over time. The algorithm detected the tip of the nose and then, a region just under it was selected. The pixel values in this region in successive images were processed to determine respiration rate. The segmentation method, used as part of the facial tracking, was evaluated on 55,000 thermal images recorded from 14 subjects with different extent of head movements. It separated the face from image background in all images. However, in 11.7% of the images, a section of the neck was also included, but this did not cause an error in determining respiration rate. The method was further evaluated on 15 adults, against two contact respiration rate monitoring methods that tracked thoracic and abdominal movements. The three methods gave close respiration rates in 12 subjects but in 3 subjects, where there were very large head movements, the respiration rates did not match.

A new sub-threshold level shifter for ultra-low voltage digital systems is presented in this study. The self-controlled supply feedback loop is quintessential for this circuit. Measured results from a test chip show that it is capable of realising a voltage conversion from a voltage as low as 0.1–1.2 V reliably, while maintaining an operational frequency of 25.2 kHz, when implemented in a 65-nm process technology. In addition, it also has ample process variation tolerance and low static power consumption. To support multi-voltage digital systems, the proposed level converter can up-convert an input at any voltage with this range to normal voltage domains.

This study presents design methodologies for high accuracy baseband detectors for use in automatic gain control (AGC) loops. These loops are used in many applications to stabilise the signal level in a transceiver chain. In a wireless frequency modulated continuous wave (FMCW) radar receiver for example, it is desired to maintain a constant baseband signal level at the receiver output prior to the analogue-to-digital converter. Due to the AGC loop feedback action, the accuracy of this output level directly depends on the detector accuracy. In this study, a detector design employing inherent cancellation of process, voltage and temperature (PVT) variations without the need for any complex compensation schemes is proposed. Measurement results of a fabricated test chip are in good agreement with simulations achieving ±0.15 dB accuracy over temperature, supply and part-to-part variations. The fabricated detector prototype on an IBM 0.18 µm technology has an active area of 0.05 mm² and draws 1 mA from a 3 V supply. An integrated AGC loop including the proposed detector achieves a 52 dB dynamic range consuming an overall 9 mW power. To the best of the authors’ knowledge, the proposed detector has the highest uncalibrated accuracy reported up to date.

M-PSK (phase shift keying) modulation schemes are used in many high-speed applications like satellite communication, as they are more bandwidth and power efficient compared with other schemes. This study presents very large scale integrated circuits (VLSI) architectures for modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK and 16PSK systems, based on the principle of direct digital synthesis. The proposed modulators do not use any multiplier in contrast to the conventional modulators and hence they are relatively fast and area efficient. Based on the coherent detection technique, this study proposes new demodulation algorithms for 8PSK and 16PSK systems which can be implemented both in analogue and digital domains. This study also presents VLSI architectures for all the proposed algorithms. The proposed architectures are described in Verilog and implemented on Xilinx field programmable gate arrays (FPGAs). The simulation results verify their functional validity and implementation results show the suitability of the proposed architectures for satellite communications.

This study presents a new complementary metal–oxide–semiconductor (CMOS) structure for a fully balanced four-terminal floating nullor (FBFTFN) which is suitable for ultra-low-voltage and low-power applications. This structure employs a bulk-driven quasi-floating-gate (BD-QFG) metal–oxide–semiconductor transistor technique to provide the capability of ultra-low-voltage, low-power operations as well as extended input voltage range. The functionality of the proposed circuits is demonstrated through simulations using SPICE and TSMC 0.18 µm n-well CMOS technology with supply voltage of 0.5 V and dissipation power of 9.4 µW. To confirm the attractive features of the proposed circuit, the fully balanced filters such as band-pass Sallen–Key filter, voltage-mode universal biquadratic filter and current-mode sixth-order low-pass filter using proposed BD-QFG FBFTFN as active elements have been designed.

This paper addresses the behavioural modelling of digital integrated circuit buffers for performance assessment of high-speed data links. A new modelling technique, with several important advantages is described. All the requirements of black-box identification are met: the approach relies exclusively on the observation of the external port voltages and currents, thus allowing the extraction of models that mimic the operation of real devices without insight on their internal structure. Furthermore, unlike the standard algorithms currently used in EDA tools, the method described in this study provides a straightforward solution to modelling the input–output behaviour. Good model performance in overclocking conditions is an important advantage. This study also investigates the possibility of accounting for power-supply voltage variations and provides a simple solution.