Graphene nanoribbon field effect transistor is considered as a next-generation device. In this study, effect on device performance parameters such as on and off state currents, cut-off frequency, delay and transconductance at different source and drain (S/D) doping concentrations is investigated. It is observed that changing the S/D doping concentrations has an impact on band-to-band tunnelling which affects the device performance. This study also reveals that the minimum conductivity point, i.e. Dirac point decreases with increase in doping concentration. The obtained results are based on non-equilibrium Green's function formalism, along with p_z orbital band model. Poisson's equation solver is used to calculate the electrostatic potential. The results obtained show that the device performance greatly depends on the S/D doping concentration.

Using embedded thermal sensors, high-performance microprocessors employ dynamic thermal management techniques to measure runtime thermal behaviour so as to prevent thermal runaway situations. However, on-chip thermal sensors are highly susceptible to noise, which results in a higher probability of false alarms and unnecessary responses. In this study, the authors propose a set of methods based on principal component analysis (PCA) to address the problem of recovering precisely the full thermal map from the on-chip thermal sensors when the sensor readings have been corrupted by noise. The authors utilise simulated annealing algorithm to devise method that determines the optimal thermal sensor locations, which can obtain superior results compared with the available literature. On this basis, the authors also propose a practical method for full thermal reconstruction to estimate the accurate temperatures of full chip, which would not need to know a-priori temperature information at each spatial distribution of thermal map. The experimental results confirm that the authors’ proposed methods are stable in the case of noisy thermal sensor observations, which can achieve a high fidelity thermal monitoring.

High electron mobility transistors (HEMTs) play a crucial role in microwave low-noise amplifier (LNA) and are used in radar receiver, software defined radio and digital radio frequency. A novel technique is used to design and fabricate a high-performance wideband LNA for 5.4–5.9 GHz based on fully stabilised InGaAs pseudo-morphic HEMT (pHEMT) 0.15 µm technology. With the Agilent Advanced Design System simulation tool, a C-band (5.4–5.9 GHz) two-stage LNA using pHEMT based on monolithic microwave integrated circuit (MMIC) technology has been designed: noise figure <1 dB, power gain of 18 dB, output 1 dB compression >13 dBm and OIP3 >24 dBm, lower value of input/output return loss reflects the accuracy of impedance matching network at input and output sides of amplifier, full band unconditional stability. In this study, it is shown that the InGaAs pHEMT has the ability to handle high power to make it the perfect technology candidate for highly survival radar receiver component and survival up to 37 dBm input power level is demonstrated. The circuit based in the proposed technology shows comparable low noise figure, decent gain, with high dynamic range and high survivability. Finally, the simulation results and fabricated device results are in good agreement and superior than the earlier reported design.

Digital pulse width modulation (DPWM) is the main process involved in power conversion of digitally controlled switching power converters. Sampling frequency of analogue to digital (A/D) converter and clock frequency of digital controllers are the two constraints which create time delay in output of the modulator gating pulses. Time delay produces the major effect in terms of low frequency oscillations when the converter operates at high switching frequency. In this study the effect of sampling frequency and clock frequency has been analysed in time domain. The aim of this study is to develop instantaneous mathematical equations for DPWM output, rising edges delay, falling edges delay and develop the analytical method through which the effect of sampling frequency and clock frequency can be minimised. The uniform multisampling technique has been used to develop the mathematical equations for different types of carriers. The clock frequency has been considered for higher frequency operation of the converters. The modulator delay depends upon the sampling frequency, clock frequency, modulation index of modulating to control signal, and the rate of change of the modulating signal. The analytical results are verified through the Xilinx system generator MATLAB/Simulink simulation, and the laboratory experimental results.

Large current sensing in a high-voltage (HV) battery module or string is hard to be realised on-chip. Thus, it is a disadvantage for the system to be miniaturised. A current sensor with a HV sense stage on silicon for HV battery modules is designed and analysed in this investigation. The proposed HV current sensor takes advantage of HV CMOS processes and resolves the problems caused by the voltage drop limitation thereof. The design methodology and analysis, including aspect sizes, are also presented. The physical on-chip and system measurement of the proposed HV current sensor demonstrates maximum error ≤ ±0.7% provided that the sensing voltage is 36–55 V, and the sensing current is 0.5–2.2 A.

In this study, the analogue performance of radio-frequency (RF) range amplifiers and ring oscillators designed using fully depleted silicon on insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied for different back oxide (BOX) thickness. The analysis exemplifies the need for BOX thickness variation analysis for the superior analogue/RF performance. The analogue parameters of the circuit analysed for different BOX thickness are the bandwidth, the linearity and the power consumption. The study shows that for an FDSOI MOSFET-based amplifier circuit, with increasing BOX thickness the bandwidth increases and the gain decreases. Also an optimum value of gain–bandwidth product for the amplifier is proposed considering the BOX thickness and the gate length of the device. It is also shown that frequency of oscillation for the ring oscillators increases with increasing BOX thickness.

This paper presents a new time-efficient modelling approach for UHF Dickson rectifiers. Due to the very low computation time, the approach can provide a quick and effective alternative to the standard transient simulations. The presented approach results in better estimation of the generated DC voltage and power conversion efficiency compared with the similar works in the literature. For the first time, an accurate mathematical relationship, including the non-zero reverse current, is expressed for finding the open load voltage of the Dickson rectifier while covering the broad range of RF amplitudes. The model uses the relation between the peak forward current and the load current to develop an input-to-output formula. Unlike the previous works, the channel length modulation is taken into consideration for the first time making the proposed model ideal for UHF Dickson rectifiers implemented with submicron CMOS transistors. Moreover, the proposed model takes secondary effects, such as the body effect and short-channel effects into account resulting in a more accurate estimation of the generated output DC voltage. Using the presented approach, a Dickson rectifier working at 900 MHz is implemented in a 0.18 µm CMOS process. Good agreement between simulation results, predicted results, and measurement results is observed.

Engineering change order (ECO) is a technique commonly used in the later integrated circuit design stages to reduce redesign efforts and time-to-market. ECO problems are generally categorised according to functional changes (functional ECO) or timing violations (timing ECO). This study differs from conventional approaches in its adoption of a solution that involves unifying functional ECO with timing ECO. The authors applied the concept of virtual nodes to the problem of transforming timing ECO into functional ECO. In addition to buffer insertion and gate sizing, the authors developed a novel detour reduction method for the repair of timing violation paths. Technology mapping is used to facilitate the selection of spare cells, through the generation of various revisions for each ECO. The unified ECO problem is then solved using a novel modification of the Hungarian matching algorithm. Experiment result demonstrates the efficacy of the proposed approach at solving both types of ECO simultaneously.

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS technologies for digital, analogue and RF designs. However, it has been demonstrated by several researchers that TFET circuits face increased on-state Miller capacitance effect, which leads to poor transient characteristics with large overshoots and undershoots. This would minimise the reliability of TFET circuits though energy efficient. This work gives more design insights (optimal sizing, number of stages, supply voltage) into TFET circuit reliability and proposes a TFET based circuit interaction design approach for ultra-low power and reliable ring oscillator circuit design. It has been shown that TFET circuit designs without proper reliability enhancement techniques such as circuit interaction or co-design approach exhibits very large undershoots/overshoots (∼20–50%). The proposed TFET circuit co-design approach (i.e. differential topology based design in comparison with the complementary static TFET logic designs) enhances the TFET circuit reliability by minimising the undershoots/overshoots to less than 0.5% with a trade-off in operating frequency and power consumption.

This study presents new prototyped evaluation results for the authors’ proposed power analysis attack countermeasure architecture based on decoupling individual sensitive modules with low current consumption. The proposed architecture includes a switch box module to randomise internal connections, mixing residual information that may leak through non-ideal switch elements and uneven charge cycles. The two implementations evaluated are a printed circuit board (PCB) developed using stand-alone CMOS components and the post-layout simulation of a circuit developed in 0.18 µm TSMC CMOS technology using Cadence. Both systems were able to protect a decoupled 8-bit XOR module from a correlation power analysis performed using traces collected at the power supply rail for at least 8000 plaintext inputs. The results show that the countermeasure is suitable for both on-chip and on-board designs. Analysis of the measurements collected from the PCB test system demonstrates the need to balance the charge/discharge frequency of the decoupling elements against the operational frequency of the decoupled modules. From the layout, an individual decoupling element was found to be similar in size to the decoupled 8-bit XOR module, with all four decoupling elements occupying a total of 51% of the layout area. This percentage is expected to decrease in the context of larger, more complex systems.

The recent development in high gain DC–DC converters motivates its application on renewable energy systems with low output voltage such as photovoltaic cells resulting in the requirement of high voltage gain converters with improved static and dynamic characteristics. This study proposes an optimal reduced order linear quadratic regulator controller for a reduced order model of a voltage multiplier cell (VMC) integrated boost converter with two sensors for measuring the output voltage and the input inductor current. The dynamic performance of linear quadratic regulator controller over load, line and component perturbations are shown through extensive simulation studies on the reduced order model developed and the comparison is accomplished with conventional hysteresis current controller in order to disclose the best control technique in terms of dynamic response. The extensive analysis based on simulated results are verified exactly with a measured results in a 100 W prototype operating in continuous conduction mode VMC integrated boost converter controlled using DSPIC30F4011 processor. The control technique proposed computes error coefficients with less computation time, guarantees excellent system stability and offers improved dynamic characteristics for VMC integrated boost converter with reduced number of sensors.