Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel-level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from high energy consumption and performance bottleneck when trying to exploit the KLP because of poor resource utilisation caused by insufficient flexibility. In this study, the authors propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilisation focusing on the kernel-stream type of the KLP. In addition, they introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream based on the RSF. Experimental results show that the proposed approaches improve performance by up to 88.8% and reduce energy by up to 48.2% when compared with the conventional CGRA-based multi-core architectures.

Power distribution network (PDN) design in three-dimensional integrated circuit (3D IC) is one of the most important challenges. Power wires and power bumps or power through-silicon-vias (TSVs) are the two major factors that affect the voltage as the IR-drop of 3D ICs. Different parameters of power wires and different insertions of power bumps/TSVs cause different IR-drop distribution. In this study, the authors propose 3D power concurrent optimisation to achieve a multi-objective design for 3D IC PDN, which optimises the insertion of power bumps/TSVs according to the IR-drop distribution and concurrently reduces the power wire's routing area so as to lower the metal coverage rate, guaranteeing the IR-drop and other constraints. Results of the experiments show that the proposed method can get more solutions than one after a run with both less power routing area and less number of power bumps/TSVs. In addition, the experiments also show that it is more effective and efficient than the classical exhaustive method.

Radio-frequency (RF) circuits employing periodically gated switches can be difficult to characterise in the frequency domain because they are time variant. The time variance causes frequency mixing and makes impedances difficult to define. A new method of frequency-domain analysis for periodic switching circuits is proposed in which a switch is represented by a matrix of admittance values. The columns of the admittance matrix correspond to voltage frequencies and the rows correspond to current frequencies, facilitating frequency translation effects in the circuit. The frequency domain is considered using a discretised set of harmonically related frequencies. The method is applied to the design and analysis of an RF switching mixer to demonstrate its advantages in calculating impedances and tuning the frequency response.

Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.

This study presents the detailed design and analysis of a new memristor-based look-up table (LUT) for field programmable gate arrays (FPGAs). The proposed memory utilises memristors as storage elements with N-type metal–oxide–semiconductor transistors for row access. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation. The proposed method requires a RESTORE pulse only for the READ 0 operation. Moreover, the WRITE operation of the proposed method requires three power lines and a RESTORE pulse only for the READ 0 operation, thus saving 25% READ time when compared with previous methods. In addition, the proposed method does not require the REFRESH pulse and does not dissipate power during stand-by mode. Extensive simulation results are presented with respect to different operational features such as normalised state parameter, pulse width and LUT size. In addition to a circuit-level evaluation, the proposed LUT scheme has also been assessed with respect to FPGA implementation. Simulation results using sequential benchmarks mapped on Spartan 4 and 5 FPGAs show that the proposed non-volatile LUT outperforms existing static random access memory cell-based LUTs in terms of performance.

Design of ultrasonic signal processing systems requires a paradigm shift to fully utilise the benefits of recent advancements in the field of integrated circuits. It is necessary to design a standardised common platform that provides the flexibility to develop both software and hardware solutions. This enables the user to explore the full design space including software only, hardware only, and hardware/software co-design. To fulfil this purpose, the authors introduce the reconfigurable ultrasonic system-on-chip hardware (RUSH) platform. RUSH provides a common basis which significantly reduces the effort required to develop an ultrasonic signal processing system able to process the full range of ultrasound from 20 kHz to 20 MHz. Furthermore, this study aims to make the design and implementation of signal processing algorithms in embedded software and reconfigurable hardware very efficient. To demonstrate the computational efficiency and design flexibility of the RUSH platform, several important computationally intense algorithms such as split spectrum processing, chirplet signal decomposition and coherent averaging have been successfully ported to the RUSH platform, emphasising the many parts of the RUSH architecture.

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 µm) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm². A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 × 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 × 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 × 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.

A defect-oriented built-in self-test (BIST) structure of charge-pump phase-locked loop (CP-PLL) for high fault coverage and low area overhead test solution is proposed. It employs a new structure of phase/frequency detector, a D flip-flop and some existing blocks in the PLL as the input stimulus generator and fault feature extracted devices for testing evaluation. Thus, no extra test stimulus or high-performance measured instruments are required for test. The structure is easily implemented and has a little influence on the performance of CP-PLL. Fault simulation results indicate that the proposed BIST structure has high fault coverage (98.75%) and low area overhead (0.78%).

In ultrasound systems synthetic transmit aperture and phased array imaging are widely used for obtaining the high quality images. These imaging systems require dynamic focusing of the multi-element transducer array at large number of scan points during transmission and reception. The array can be focused at any point by applying proper delay values to the signals, received or transmitted by each element of the array. Dynamic focusing requires on-line computation of the delay values, for large number of scan points, corresponding to all the elements of the array. This paper describes a delay calculation algorithm and corresponding hardware architecture for dynamically focusing the convex transducer array at large number of scan points. The hardware architecture for the 64-element convex transducer array, which scans 128 scan lines having 1024 scan points on each scan line, consumes 61k gates. It shows around 57–86% improvement in terms of hardware consumption with respect to those of other available architectures. To reduce the overall complexity and latency of the delay calculator, a 28- bit radicand square root calculator architecture which requires less initial memory than that of the linear approximation and less hardware resources than that of the quadratic approximation is also presented.

This paper presents a set of novel two-parallel pipelined fast Fourier transform architectures for discrete Fourier transform computation of real-valued signal. The previous approaches of designing real-valued fast Fourier transform (RFFT) architectures are the attempts made to make the data path real. Some of the previous designs have partial real data paths (only first two stages are real), whereas the other designs have complete real data-paths, but reordering registers are required to bring the real and imaginary parts in parallel. Hence, these approaches reduce the number of registers and butterflies only to some extent in the RFFT design. In the proposed designs, feedback-based scheduling structures are introduced, which reduce the number of registers to half in several stages when compared with the previously known designs. Therefore, the proposed designs require 30% less area and 31.5% less power than the prior designs.

The low- and mid-frequency model of the transformer with resistive load is analysed for different values of coupling coefficients. The model comprising of coupling-dependent inductances is used to derive the following characteristics: voltage gain, current gain, bandwidth, input impedance, and transformer efficiency. It is shown that in the low- and mid-frequency range, the turns ratio between the windings is a strong function of the coupling coefficient, i.e., if the coupling coefficient decreases, then the effective turns ratio reduces. A practical transformer was designed, simulated, and tested. It was observed that the magnitudes of the voltage transfer function and current transfer function exhibit a maximum value each at a different value of coupling coefficient. In addition, as the coupling coefficient decreases, the transformer bandwidth also decreases. Furthermore, analytical expressions for the transformer efficiency for resistive loads are derived and its variation with respect to frequency at different coupling coefficients is investigated. It is shown that the transformer efficiency is maximum at any coupling coefficient if the input resistance is equal to the load resistance. Experimental validation of the theoretical results was performed using a practical transformer set-up. The theoretical predictions were found to be in good agreement with the experimental results.

In this paper, the performance of asymmetric self-cascode (A-SC) fully depleted silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistors configuration applied to common-source current mirrors (CMs) have been analysed through experimental measurements, comparing with symmetric self-cascode configuration as well as with standard uniformly doped transistor. The mirroring precision, output resistance and output swing have been used as figures of merit to evaluate the improvements achieved with the use of A-SC transistors. Two-dimensional numerical simulations have been also performed in order to further explore the advantages of A-SC transistor in common-source CMs. The obtained results have shown that the best mirroring precision has been obtained with larger channel lengths of the transistor near the source. Despite the worsened intrinsic mismatching presented by common-source CMs implemented with A-SC transistors in comparison with single transistor CM, the A-SC structure has allowed larger output resistance, breakdown voltage and better mirroring precision.