This study presents the design of current-mode full-wave rectifier circuits using single active component. The first proposed circuit uses only one operational transconductance amplifier (OTA), two diodes and two resistors. Its current gain can be electronically controlled using the transconductance gain of the OTA. The second proposed circuit uses only one differential voltage current conveyor (DVCC), two diodes and three resistors. Using the complementary metal-oxide semiconductor structure of both OTA and DVCC, the behaviours of the proposed structures have been verified by HSPICE simulations. In addition, both of the proposed circuits are tested practically using commercially available components, such as AD844 and LM13700.

Charge pumps (CPs) represent the most common solution for the implementation of fully integrated DC–DC converters. In fact, as opposed to buck/boost DC–DC converters, that need at least an external inductor, charge pump circuits do not require any external component. However, the achievable power efficiency of these circuits is typically significantly lower than power efficiency of buck/boost DC–DC converters. In this study, we develop a general mathematical model of CPs, aiming to provide basic design considerations for power efficiency optimisation. A quality factor for achievable power efficiency is proposed together with guidelines for the design of efficiency-optimised CPs under the constraint of given output voltage and current values.

This study presents a two-switch continuous conduction mode pulse width modulation flyback converter that employs an LC snubber circuit. The snubber circuit is used to achieve zero voltage switching (ZVS) operation for the main switches during the turn-off transition and soft switching for power diodes. With the proposed LC snubber, the magnetic energy in the transformer leakage inductance can be fully recycled and transferred to the input side. The resonant circuit consists of a resonant inductor, a resonant capacitor and two diodes. The operating principles, theoretical analysis and the design methodology of ZVS two-switch continuous conduction mode (CCM) flyback converter are presented. A 200 W (50 V/4 A) laboratory prototype of the proposed converter, operating at a switching frequency of 300 kHz is built to verify the theoretical analysis. At full load the efficiency is 94%.

Continuous-time (CT) delta-sigma (Δ∑) analog-to-digital converters (ADCs) have one important constrain, namely the excess loop delay. Most excess loop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distributed random variable. To improve system performance with the same loop filter, a new compensation algorithm for the excess loop delay of CT Δ∑ ADCs based on the model matching method is presented in this study. Compared with previous compensation methods, the model matching algorithm is more practical because the value of the excess loop delay varies randomly every clock period. It is shown through simulation that a mean value based algorithm can improve the SQNR performance of CT Δ∑ ADCs for the most probable values of the excess loop delay.

A simple and robust self-healing technique for millimetre-wave (mm-wave) amplifiers is proposed. The self-healing technique can correct the operation frequency shifting of the amplifier (including its input and output impedance matching shifting) due to process, voltage, and temperature variations and modelling inaccuracy. A mm-wave amplifier with digitally controlled artificial dielectric transmission lines as fine frequency tuning components and an on-chip power detector as the frequency shifting detector has been implemented in 65 nm complementary metal–oxide–semiconductor to verify the effectiveness of the technique. The operating frequency of five amplifier chips is calibrated by running the self-healing algorithm on a field-programmable gate array development board. On average, the gain of the amplifier is improved by 2.60 dB from 13.66 to 16.26 dB and the input matching is improved by 12.78 dB from −4.89 to −17.67 dB at 56 GHz after the proposed self-healing procedure.

The reliability of three-dimensional (3D) integrated circuit (IC) is dependent on the yield of through silicon vias (TSVs). Moreover, the highly inductive nature of TSV lead to significant Ldi/dt drop especially in the power distribution network, therefore reduction in loop inductance is sought for curtailing Ldi/dt drop. In this study, the authors explore the grouping of thinner TSVs to replace a thick TSV (with identical current carrying capability) to reduce the loop inductance of TSVs and provide added redundancy. Closed-form mathematical equations are derived to calculate resistance inductance capacitance (RLC) parasitic of grouped TSVs. To the best of the authors’ knowledge, this is the first work towards investigating the grouping of thin TSVs to quantitatively analyse the exploits of their lower inductance and inherent redundancy. Their simulation results for power distribution network of 3D IC using conventional TSV and proposed grouped TSV showed that Ldi/dt drop improves from minimum of 9% in conventional design to up to 0.08% in the proposed design.

Ultrasonic industrial and medical imaging applications involve acquisition of large amount of volumetric data in real time. Therefore, data storage becomes critical in many current day applications which utilise ultrasound technology. Compressing the acquired data allows possessing minimal storage and also helps to rapidly transmit information to remote locations for expert analysis. The objective of this study is to design computationally efficient architectures for implementing discrete wavelet transform-based ultrasonic three-dimensional (3D) data compression algorithm on a reconfigurable ultrasonic system-on-chip (SoC) hardware platform. In this study, hardware and software architectures of the 3D ultrasonic compression algorithm are realised using Xilinx Zynq all programmable SoC. This study demonstrates that, compressing 33 MB of experimental ultrasonic 3D data into 0.42 MB (98.7% compression) requires only 84 ms for hardware architecture, and 1 min for software architecture, making both designs highly suitable for real-time ultrasonic imaging applications. Furthermore, the 3D compression is implemented by using Open Computing Language (OpenCL) targeted on Nvidia GT 750M graphical processing unit. OpenCL implementation of ultrasonic 3D compression algorithm completes the execution in <1 sec. This approach provides improved computational performance as that of hardware architecture, and comparable flexibility as that of software implementation.

On the basis of the quasi-linear relationship between the surface potentials of a common double-gate metal–oxide–semiconductor field-effect transistor, a compact noise model, which is adapted to gate-oxide-thickness asymmetry, is proposed. The proposed model includes a physics-based thermal and flicker noise model. The effect of the lateral and vertical electric fields on the mobility degradation has also been taken into account for accurate noise prediction in short-channel devices. The thermal noise model is compared with the technology computer aided design (TCAD) simulation data and good agreement is observed. The proposed noise model appears to be efficient for analogue circuit simulation.

A divide-by-3 injection locked frequency divider is presented. The divider works based on a two-stage differential ring oscillator in which two quadrature signals are used as injection signals. The analytical relationship for the divider locking range is derived and the main factors impacting on this parameter are discussed. The circuit has been designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V. Post layout simulation on the divider including all layout wiring parasitic elements such as resistance, capacitance and inductance shows that the typical locking range of the divider is over 3 GHz from 1 to 4.2 GHz for −0.5 dBm injection signal level while its total power dissipation for 4.2 GHz input injection signal is 505 μW at the supply of 1.8 V.

This study presents a new low-voltage (LV) supply and low-power consumption bulk-driven quasi-floating-gate fully differential current conveyor (BD–QFG-FDCCII) active element which is suitable for LV signal processing applications. The bulk-driven technique is used to achieve LV supply as low as a 0.5 V and extended input voltage swing. On the other hand, the quasi-floating-gate technique is used to achieve high-frequency performance. To prove the workability of the proposed circuit, new voltage-mode biquadratic filter and fifth-order leap-frog low-pass filter using BD–QFG-FDCCIIs as active devices have been designed and illustrated in this study. The functionality of the proposed circuits is demonstrated through PSPICE simulations using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm n-well complementary metal–oxide–semiconductor technology with a 0.5 V supply voltage and a power consumption of 16.1 µW.