Online ISSN
1751-8598
Print ISSN
1751-858X
IET Circuits, Devices & Systems
Volume 1, Issue 5, October 2007
Volumes & issues:
Volume 1, Issue 5
October 2007
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- Author(s): V. Benda
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 313 –314
- DOI: 10.1049/iet-cds:20079027
- Type: Article
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p.
313
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- Author(s): F.-J. Niedernostheide ; H.-J. Schulze ; H.-P. Felsl ; T. Laska ; U. Kellner-Werdehausen ; J. Lutz
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 315 –320
- DOI: 10.1049/iet-cds:20060369
- Type: Article
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p.
315
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Recent activities in insulated gate bipolar transistor (IGBT) and thyristor development focus on the integration of protection functions in order to improve the reliability of the entire electronic system. It is shown how various protection functions can be integrated into symmetric and asymmetric light-triggered thyristors with a blocking capability up to 13 kV. Furthermore, different measures to provide IGBTs with an overvoltage protection are discussed and experimental results revealing the successful implementation of such a protection function are presented. - Author(s): P. Hazdra and V. Komarnitskyy
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 321 –326
- DOI: 10.1049/iet-cds:20070013
- Type: Article
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p.
321
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Enhanced formation of shallow donors (SDs) in hydrogen or helium-irradiated and subsequently annealed float‐zone n-type silicon is investigated. Ion energies, irradiation fluences and annealing temperatures were chosen in ranges typically used for local lifetime control in silicon power devices. Introduced radiation defects and SDs were investigated by deep-level transient spectroscopy and C–V profiling. Results show that radiation damage produced by helium ions remarkably enhances formation of thermal donors (TDs) when the annealing temperature exceeds 375°C, i.e. when the majority of vacancy-related recombination centres anneal out. Proton irradiation introduces hydrogen donors (HDs) which form a Gaussian peak at the proton end-of-range. Their concentration linearly increases with proton fluence and changes dramatically during post-irradiation annealing between 100 and 200°C since HD constituents are reacting with radiation damage. Their annealing in this temperature range is influenced by the electric field. If annealing temperature exceeds 400°C, HDs disappear and the excessive shallow doping is caused, as in the case of helium irradiation, by TDs enhanced by radiation damage. Shallow doping introduced by both hydrogen and helium can have a detrimental influence on blocking voltage of power diodes if high irradiation fluences or wrong annealing conditions are chosen. - Author(s): H.P.E. Xu ; O.P. Trescases ; I.-S.M. Sun ; D. Lee ; W.T. Ng ; K. Fukumoto ; A. Ishikawa ; Y. Furukawa ; H. Imai ; T. Naito ; N. Sato ; S. Tamura ; K. Takasuka ; T. Kohno
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 327 –331
- DOI: 10.1049/iet-cds:20070008
- Type: Article
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p.
327
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Vertical double diffused MOSFET (VDMOS) is an established technology for high-current power-switching applications such as automotive circuits. The most serious failure mode is destructive damage during inductive switching, resulting from avalanche breakdown of the forward-blocking junction in the presence of high current flow. Improving the ruggedness of the device is achieved by enhancing its ability to absorb inductive energy under avalanche conditions. The purpose of the paper is to explore the possibility of improving the ruggedness of VDMOS through TCAD simulations. A p+-strip buried underneath an n+-source is proposed to suppress the turn-on of the parasitic bipolar transistor. VDMOS transistors with this design modification are expected to have higher ruggedness while maintaining its superior figure-of-merit. - Author(s): Y. Weber ; J. Roig ; J.-M. Reynès ; F. Morancho ; E.N. Stefanov ; M. Dilhan ; G. Sarrabayrouse
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 333 –340
- DOI: 10.1049/iet-cds:20060371
- Type: Article
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p.
333
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A vertical N-channel 150–200 V FLYMOSFET concept has been applied on silicon: its P-buried layer introduced in the N− epitaxial region, called ‘P floating island’, is the key factor for superior performance. A particular physical characterisation technique, scanning capacitance microscopy, is used on a power device to establish 2D and 3D island representation and to go beyond 1D information given by spreading resistance profiling. Experiments including four different boron implantations of P floating islands and two different spacings of the basic cell are conducted, because the form and the concentration of the floating islands and, moreover, the spacing between them directly impact the electrical performance. Concerning the electrical study, FLYMOSFET measurements show good ‘specific on-resistance/breakdown voltage’ (RON.S–BVdss) trade-offs, better than the conventional VDMOSFETs, and UIS ruggedness as good as superjunction MOSFETs. - Author(s): I. Pawel ; R. Siemieniec ; M. Rösch ; F. Hirler ; R. Herzer
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 341 –346
- DOI: 10.1049/iet-cds:20060370
- Type: Article
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p.
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The avalanche behaviour of a new trench power MOSFET was investigated with the help of measurements and electro-thermal device simulation techniques. Two different destruction regimes were identified experimentally: energy-related destruction and current-related destruction. Possible simulation approaches to account for the different effects were proposed. The corresponding results agreed well with measurements. Furthermore, the simulations qualitatively predicted the experimental results' dependence of avalanche behaviour on design parameters. - Author(s): D.N. Pattanayak ; Y. Bai ; K. Owyang
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 347 –356
- DOI: 10.1049/iet-cds:20070021
- Type: Article
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p.
347
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The scalability of superjunction and superfield power MOSFET technologies to breakdown voltage lower than 250 V is investigated. The influence of device geometry and process architecture on the switching figures-of-merit of these relatively new classes of power switches with a breakdown voltage rating of 80 V is presented. The current flow and field distributions inside these devices are described. Using Gauss's law, the field-induced compensation of the doping density in the drift region during the blocking state of both superjunction and superfield MOSFETs is calculated from the knowledge of the lateral field distributions. It is shown that the problem associated with imperfect charge compensation at the edge of the die for a superfield effect power MOSFET structure can be avoided by using an unconventional racetrack layout design. - Author(s): F. Udrea
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 357 –365
- DOI: 10.1049/iet-cds:20070025
- Type: Article
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p.
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The current status of high-voltage power semiconductor devices and technologies for high-voltage integrated circuits is reviewed and the new trends in this field are discussed. The paper focuses on the concepts of the novel reduced surface field and state-of-the-art silicon technologies such as high-voltage silicon on insulator, which are expected to play an increasingly important role in power system on-chip manufacturing. Lateral devices such as LDMOSFETs, superjunctions and lateral insulated gate bipolar transistors are discussed. The paper also touches on emerging technologies such as unified MEMS-IC for enhanced breakdown capability and isolation. Finally, an overview of the fierce fight of technology survival in terms of specific on-state resistance against breakdown voltage is given. - Author(s): E. Napoli
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 366 –371
- DOI: 10.1049/iet-cds:20070004
- Type: Article
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p.
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The behaviour of a deep depletion (DD) silicon on insulator (SOI) lateral MOS (LDMOS) is analysed. DD of the substrate for an SOI device has been recently proposed as an innovative technique to design power devices featuring a transient breakdown higher than the static breakdown. DD is a dynamic effect that allows the design of a whole new generation of SOI power devices. Eligible applications are power conditioning circuits in which the device sustains transient voltages higher than bus voltage such as the flyback converter and the resonant circuits. Numerical simulation methods are used to analyse the behaviour of the device together with the effect of temperature, substrate carrier generation time and applied reverse bias on the duration of the transient breakdown phase. The results show that the newly proposed DD SOI device, an SOI power LDMOS using P− substrate, exhibits a static breakdown voltage of 190 V and sustains transient overvoltages up to 280 V. Furthermore, mixed-mode simulation of a complete Class E resonant converter using the proposed DD SOI device is presented. - Author(s): J. Millán
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 372 –379
- DOI: 10.1049/iet-cds:20070005
- Type: Article
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p.
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The recent progress in the development of high-voltage SiC, GaN and diamond power devices is reviewed. Topics covered include the performance of various rectifiers and switches, material and process technologies of these wide band-gap semiconductor devices and future trends in device development and industrialisation. - Author(s): M. Brezeanu ; T. Butler ; N. Rupesinghe ; S.J. Rashid ; M. Avram ; G.A.J. Amaratunga ; F. Udrea ; M. Dixon ; D. Twitchen ; A. Garraway ; D. Chamund ; P. Taylor
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 380 –386
- DOI: 10.1049/iet-cds:20060379
- Type: Article
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p.
380
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Its outstanding electronic properties and the recent advances in growing single-crystal chemically vapour-deposited substrates have made diamond a candidate for high-power applications. Diamond Schottky diodes have the potential of being an alternative to silicon p–i–n and SiC Schottky diodes in power electronic circuits. Extensive experimental and theoretical results, for both on- and off-state behaviour of metal–insulator–p-type diamond Schottky structures, are presented here. The temperature dependence of the forward characteristics and electrical performance of a termination structure suitable for unipolar diamond devices are also presented. - Author(s): D. Polenov ; J. Lutz ; H. Pröbstle ; A. Brösse
- Source: IET Circuits, Devices & Systems, Volume 1, Issue 5, p. 387 –394
- DOI: 10.1049/iet-cds:20060380
- Type: Article
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p.
387
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The transient current sharing in parallel connected Schottky-barrier diodes and MOSFET synchronous rectifiers is analysed. It is shown that, because of parasitic inductances the desired reduction of dead-time conducting losses and reverse-recovery peak current is limited, when discrete devices are used. The total amount of conducting losses in the free-wheeling circuit can increase. A reduction of switching losses in half-bridge configurations is possible because of secondary effects.
Editorial: Power semiconductors
Thyristors and IGBTs with integrated self-protection functions
Local lifetime control in silicon power diode by ion irradiation: introduction and stability of shallow donors
Design of a rugged 60 V VDMOS transistor
Characterisation of P floating islands for 150–200 V FLYMOSFETs
Experimental study and simulations on two different avalanche modes in trench power MOSFETs
Low-voltage superjunction technology
State-of-the-art technologies and devices for high-voltage integrated circuits
Limits and application of the newly proposed deep-depletion SOI LDMOS
Wide band-gap power semiconductor devices
Single crystal diamond M–i–P diodes for power electronics
Influence of parasitic inductances on transient current sharing in parallel connected synchronous rectifiers and Schottky-barrier diodes
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