A compact miniaturised-element frequency selective surface (FSS) is proposed for size reduction. The proposed structure can be considered as a common square-loop slots FSS overlaid with a periodic array of metallic patches mounted on an ultra-thin dielectric layer. A larger coupling capacitance is brought in each overlap area between the two layers of parallel metallic films. The theoretical analysis and simulation results, together with measured results, demonstrate that a much better compactness characteristic can be realised in the proposed FSS.

An absorptive frequency selective surface with a wide absorptive property over the low band and a good transmissive property at high frequency is designed. The transmission of high frequency is realised by putting a choke structure into the element to control the current distribution. Its −10 dB absorption band is from 2.8 to 8.3 GHz and the transmission band is at 9.7 GHz with insertion loss <0.5 dB. Numerical and experimental results are given.

A half-mode substrate integrated waveguide (HMSIW) omnidirectional slot antenna is proposed for the first time by integrating four narrow wall radiating slot antenna elements and a four-way power divider. The slot antenna element realises energy radiation from the open side of the HMSIW by etching several pairs of transversal slots both on the upper and the lower surfaces of the HMSIW and alternately arranging the slot pairs. A novel HMSIW four-way power divider is achieved to feed the slot antenna elements by loading four big metallic vias to guide the microwave into the HMSIW branches. This omnidirectional slot antenna has an efficiency of 86%, a gain of 5.8 dBi and an out-of-roundness of ±1.5 dB at 3 GHz, which makes it a good candidate for wireless communication applications.

A wearable hand exoskeleton (EXO) device that permits exertion of bidirectional forces on finger phalanges throughout the human finger workspace is proposed. The novelty of the proposed device lies in its direct-driven, portable and optimised mechanism with the ability to adjust variable hand sizes in addition to other distinguishing features. The adjustable link lengths and structure of the device have emerged from kinematic-based optimisation criterion, which targets the natural finger workspace. The selection of actuators for the EXO is backed by the results of experiments conducted using appropriate sensory instrumentation to measure the force exertion levels of a human hand. A four-fingered prototype of the EXO is designed and fabricated. The device is then subjected to various test inputs to characterise the tracking performance. Preliminary results demonstrate that the proposed device can flex and extend the fingers following accurate trajectories.

Magnetic resonance electrical impedance tomography (MREIT) measures the z-component of magnetic flux density B = (B_x , B_y , B_z ) induced by externally injected current through a pair of electrodes. MREIT visualises in-vivo electrical current density and/or conductivity distribution in a three-dimensional imaging object from the measured magnetic flux density B_z . MREIT techniques typically use the phase difference approach in an interleaved encoding scheme by the injection of positive and negative currents to cancel systematic phase artefacts. Developed is a method to measure B_z data using only a single scan by the injection of one current, avoiding the interleaved encoding scheme. The method separates measured multiple k-space lines into acquired k-space lines with and without injection currents and develops an algorithm to measure the magnetic flux density B_z using acquired k-space lines by the injecting current. Results from phantom experiments demonstrate that the method has potential to measure magnetic flux density using only a single scan by the injection of one current.

A threshold voltage (V _th) compensation scheme is proposed. In this scheme, the bias voltage required to compensate the V _th has been acquired from the input radio-frequency (RF) signal voltage and the output DC voltage. The proposed rectifier and the self V _th-cancellation (SVC)-based rectifier have been designed and fabricated in a standard 0.18 μm CMOS technology. Measurements have been performed for various resistive loads at the ISM 433 MHz frequency. The maximum PCE value achieved by the proposed rectifier is 30% at an input RF power level of −5 dBm whereas the maximum PCE achieved by the SVC is 22% at −9 dBm. These PCEs have been measured at a load resistance of value of 10 kΩ.

An implementation of a discrete Hilbert transformer based on half-band filters using switched-current (SI) techniques is proposed. Structurally, all-pass networks were used to build a system with very low sensitivity to transistor mismatch. A sensitivity simulation is presented to validate the proposed circuit.

Hardware implementation of the fast Fourier transform (FFT) function consists of multiple consecutive arithmetic operations over complex numbers. Applying floating-point arithmetic to FFT coprocessors leads to a wider dynamic range and allows the coprocessor to collaborate with general purpose processors via the standard floating-point arithmetic. This offloads compute-intensive tasks from the primary processor and overcomes floating-point concerns such as scaling and overflow/underflow detection. The downside, however, is that floating-point units are slower than the fixed-point counterparts. One of the popular ways to improve the speed of floating-point FFT units is to merge the arithmetic operations inside the butterfly units of a FFT architecture. This leads to a butterfly architecture based on multi-operand adders. Butterfly units are designed, in two of the most recent works, using three-operand and four-operand adders. However, the work reported here by the present authors goes further and a butterfly architecture based on a five-operand adder is proposed. Simulation results demonstrate that the proposed butterfly architecture is 50% smaller than the fastest previous work with about 17% latency overhead. Compared with the smallest previous work, the proposed design is 47% smaller and 8% faster.

A highly digital in-situ biasing solution for analogue interfaces in nanoscale complementary metal-oxide semiconductor (CMOS) technologies is presented. The digital biasing scheme uses a time-based successive approximation conversion to provide the desired analogue functions with the voltage/current input and output. The digital biasing circuit obtains benefits from scaled devices with a small dimension and a high Ft, but with no design difficulties by the advanced CMOS process. By taking advantage of ultra-compact digital logic for control and adaptation, the digital biasing circuit does not suffer from the impact of intra-die variations since it eliminates the need for shared biasing approaches. A digital common-mode feedback circuit (CMFB) for a fully differential amplifier was simulated to demonstrate the advantages of the digital in-situ biasing scheme. The digital CMFB designed in a 65 nm CMOS process provides a desired output common-mode voltage as a conventional analogue CMFB, but does not need any stability compensation schemes. Compared with the analogue CMFB, the digital CMFB with the digital-like structure is more robust, has much smaller area, and does not require large passive components.

A feedback-based weight programming method for a high-density crossbar without the use of any transistor or diode isolation is presented. A series of reads is applied to the crossbar before each write that is able to determine the resistance of each memristor in the crossbar despite the many parallel resistance paths. This is essential because the variation observed in memristor crossbars makes programming very difficult when using just a single write pulse and no error checking. A neuromorphic circuit is programmed using this method. Results show successful ex-situ training of a high-density crossbar with significant area savings when compared with a one transistor one memristor design.

A novel 10 Gbit/s source-series-terminated (SST) transmitter in 65 nm CMOS technology is presented. Different from the conventional SST transmitter with the swing fixed to the supply voltage, the proposed transmitter, employing modified SST topology with switch-based shunting legs, achieves tunable swing to provide suitable a output voltage for specific channel loss, resulting in higher power efficiency for the short and medium-length channel. The proposed de-emphasis scheme operates with the shunting path connecting the differential output pins instead of the voltage supply and the ground, which is more efficient than the conventional way. Fewer slices for de-emphasis are needed along with less parasitic capacitance, and thus the power efficiency is improved. A full-rate delay-matching pre-driver is used to avoid a complicated structure. Swing ranges from 50 mV to 1.2 V at a 1.2 V supply. The de-emphasis could be tuned from 0 to −15.5 dB with power consumption dropping from 15.6 to 13.3 mW at the nominal swing of 1.2 V.

Ordinal hyperplane ranking achieves superior performance in facial age estimation. However, further experiments show that this approach suffers from its ideal ranking rule, which sometimes causes unnecessary estimation deviations and degrades performance. Two approaches with new ranking rules are proposed, which minimise accidental deviations of binary classifiers and tactfully combine the accuracy and obtained label in each binary classification substep for the ranking criteria. Moreover, at first the extreme learning machine is introduced into facial age estimation, taking full advantage of its high learning speed and accuracy. Experimental results from public datasets are presented to demonstrate that the proposed algorithms reduce the mean absolute error and improve age estimation performance while reducing runtime significantly.

Multilabel image annotation is one of the most important open problems in the computer vision field. Unlike existing works that usually use conventional visual features to annotate images, features based on deep learning have shown potential to achieve outstanding performance. A multimodal deep learning framework is proposed, which aims to optimally integrate multiple deep neural networks pretrained with convolutional neural networks. In particular, the proposed framework explores a unified two-stage learning scheme that consists of (i) learning to fune-tune the parameters of the deep neural network with respect to each individual modality and (ii) learning to find the optimal combination of diverse modalities simultaneously in a coherent process. Experiments conducted on a variety of public datasets.

A novel check node unit architecture for low-density parity check (LDPC) decoders, which avoids the usage of carry-based comparators for the computation of the required first and second minimum values, is presented. It relies on a one-hot representation of the input messages’ magnitude, obtained by q-to-2 ^q decoders. The two minimums are computed using an OR tree and a modified leading zero counter. The proposed architecture is imprecise, as the second minimum is not computed correctly when it is equal to the first one. The implementation results and the analysis of the error correction capability show that the proposed imprecise unit is highly suited for high rate LDPC codes; it presents up to 30% better hardware cost, a higher working frequency, while the loss of the decoding capability is negligible with respect to standard implementations.

A dual-mode dynamic/static (dynastat) divided-by-two combines the range of a static frequency divider (DC-117 GHz from simulation) and the higher toggle frequency of a dynamic divider (85–153 GHz, simulated) at a low input sensitivity of 0.2 V_pk differential (<−3 dBm into 50 Ω). The measured self-oscillation frequencies of the prototype are 79 GHz (static) and 129 GHz in dynamic mode. The 8880 μm² dynastat implemented in 90 nm silicon germanium (SiGe)-bipolar CMOS consumes 38 mA (static) and 19 mA (in dynamic mode) from a 4.5 V supply.

A 90° fine tuning phase shifter design with low insertion phase-variation a VGA for V-band phased array systems is presented. The vector-sum phase shifters require low phase-variation VGAs with a gain control range of about 10 dB for good digital control performance. The measured data for discrete devices have found that a cascode has 20° better phase variation performance than a common source in the required gain control range at 50 GHz. To demonstrate the design, the Ku-band scaled phase shifter has been fabricated in 0.13 µm standard CMOS process. It consists of 90°/0° hybrids with lumped elements and two cascode VGAs. The 91° continuous phases with the gain of 2.7 ± 0.9 dB are obtained at 13 GHz.

A dual-passband low-temperature co-fired ceramic (LTCC) filter with a stacked quarter-mode substrate-integrated waveguide (QMSIW) and an eighth-mode SIW (EMSIW) on LTCC substrates is presented. By exploiting the QMSIW and EMSIW cavities, the filter has a dual passband with high selectivity and compact size. The experimental filter exhibits two passbands, one is centred at 5.4 GHz with an insertion loss of <1.7 dB, and a 3 dB bandwidth of 13%. The other is centred at 8.3 GHz with an insertion loss of <1.5 dB, and with a bandwidth of 12.9%. The volume of the filter is only 6.5 × 6.5 × 1.2 mm³.

A suitable method is introduced to improve the isolation of slot-coupled directional couplers. The proposed coupler consists of two trapezoidal-shaped patches that are coupled through a trapezoidal-shaped slot in a common ground plane. The inherent phase velocity differences between the even- and odd-modes of the slot-coupled directional coupler are compensated around the centre frequency of the coupler by introducing some slots to the trapezoidal-shaped patches. A design graph is derived by sweeping some dimensions of the coupler. A hatched area is also added to the design graph that indicates the appropriate coupler dimensions which lead to the equal even- and odd-mode phase velocities around the centre frequency. To demonstrate the effectiveness of the proposed coupler, an 8 dB coupler operating from 1 to 3.3 GHz is designed and constructed. The measurement results are in good agreement with the simulation results. The results show that the isolation of the designed coupler has improved significantly in comparison with the other designed coupler with no cut slots in the patches.

The first quadrature phase shift keying (QPSK) data link at 385 GHz, using a photonic-based terahertz (THz) emission and a double heterodyne THz detection, is reported. The QPSK signalling is investigated up to 16 Gbaud (32 Gbit/s) on a short range distance, with 20 µW received power levels.

Integrated dynamic bandwidth allocation with an overlap scheme that improves the bandwidth efficiency of aggregated access networks is implemented and demonstrated on the 10 G Ethernet passive optical network (EPON)-based prototype system for the first time. Experiments revealed that the prototype system can achieve more than 99% bandwidth efficiency with only 150 kB aggregation buffers in each optical subscriber unit.

Terahertz-frequency quantum cascade lasers (THz QCLs) have numerous potential applications as 1–5 THz radiation sources in space science, biomedical and industrial sensing scenarios. However, the key obstacles to their wide-scale adoption outside laboratory environments have included their poor far-field beam quality and the lack of mechanically robust schemes that allow integration of QCLs with THz waveguides, mixers and other system components. A block integration scheme is presented, in which a continuous-wave ∼3.4 THz double-metal QCL is bonded into a precision-machined rectangular waveguide within a copper heat-sink block. This highly reproducible approach provides a single-lobed far-field beam profile with a divergence of ≲20°, and with no significant degradation in threshold current or in the range of operating temperatures.

A low-power pseudo-random bit sequence (PRBS) generator for testing a high-speed optical transmitter module has been realised in a 130 nm bipolar CMOS process. The transmitter consists of a monolithic driver circuit architecture and a heterojunction bipolar transistor (HBT)-based carrier-injection electro-absorption modulator. A 10 Gbit/s current mode logic latch with only 0.6 mW power consumption is designed by scaling down the current density without degrading the overall transmitter speed performance. The 2⁷−1 PRBS generator circuit consumes only 42.75 mW at 6 Gbit/s operating speeds with a 1.5 V dc power supply. The core circuit power consumption is 9 mW.

The non-destructive observation of ferroelectric domain inverted (DI) structures in magnesium oxide (MgO)-doped lithium niobate (LiNbO₃) crystals by a scanning electron microscope is reported. The secondary electron emission coefficient dependent on the acceleration voltage is measured to find the second cross-over voltage. The surface potential contrast formed by the pyroelectric charge was observed. The high-contrast images of DI structures of 15 μm period for quasi-phase matching is obtained in the telecom wavelength band.

A novel design of a simple and compact tunable fibre laser that uses the chromatic aberration of the lens relay and a slit-like effect of the optical fibre core is proposed and demonstrated. The tunability of 20 nm is obtained by 130 µm of cavity output mirror adjustment.

For demonstrating autonomous operation of the Internet of things (IoT) smart sensors, the compact folded dipole rectenna with radio frequency (RF) energy harvesting is proposed. The rectifying circuits in the proposed rectenna consist of the impedance matching network and the voltage multiplier for the optimised received power. It has achieved the RF-dc conversion efficiency of approximately 23% when illuminated by a radio signal of 1 mW available power from the commercial UHF RFID reader.

An improved transformer circuit model is proposed for performing a more accurate analysis of LLC dc–dc converters. In the proposed model, the inductances and turns ratio are expressed by a coupling coefficient k. With the help of newly defined parameters for the transformer, voltage gain and switching frequency can be predicted with high accuracy and therefore it becomes possible to design a considerably practical design of the LLC dc–dc converter. The validity of the analysis method using the proposed transformer circuit model is verified by experimental results with a 500 W prototype.

The derivation of the equation for the minimum value of magnetising inductance needed for the multiple-output flyback DC–DC converter to operate in continuous-conduction mode (CCM) is presented. The equation is derived for two outputs and then generalised for multiple outputs. Two design examples are presented, one for equal output voltages and the other for unequal output voltages. Simulation results are presented in order to verify the derived expressions.

A procedure to evaluate the power transfer efficiency of ultra-high-frequency (UHF) radio-frequency identification (RFID) passive systems is presented. The ratio between the available power at the tag antenna and the input power into the reader antenna is measured for the first time in the UHF RFID frequency band. The power absorbed by the tag antenna is measured using a transition and matching circuit.

The frequency modulated continuous-wave (FMCW) technique has been used in many radar applications owing to its low requirements on radar hardware. Linear sawtooth sweep (the frequency sweeps in one direction) is one of the simplest waveforms employed by most FMCW radars. By theory and real data it is proved that by simply using the linear triangular sweep (the frequency goes first down and then up), the range resolution can be doubled without increasing the transmitted bandwidth.

In boundary zones (edges) in synthetic apertue radar (SAR) images, there is no logical (scientific) explanation for employing the kernel average for approximating the backscattering factors in central kernel pixels. Therefore, adaptive filters are used to decrease the speckles in these images. These filters prevent the averaging process in the edges when smoothing the images (noise reduction) in homogeneous areas, thus causing reduction of lucidity in the edges. In most existing adaptive filters, the variation coefficient (coefficient of variation) is used to detect the edges in the images. An alternative factor is introduced to detect the edges in intensity images; by employing this factor, an adaptive filter is presented. The results of evaluating this filter and comparing it with other adaptive filters illustrate that it has excellent competency in speckle reduction, and hence it protects the edges of the images during the filtering process. using various assessment measures (such as signal-to-noise ratio and mean absolute error), the obtained results provide evidence that the proposed filtering process outperforms other classical methodologies.

In compressed sensing (CS)-based inverse synthetic aperture radar (ISAR) imaging for aircraft, the image of the target can be reconstructed using fewer pulses with random pulse repetition intervals than with the conventional range-Doppler (RD) method. However, the micro-Doppler (mD) effect induced by the non-stationary parts of aircraft still causes defocusing as in RD imaging. A method is proposed to reduce the mD effect in CS ISAR imaging. The CS-based short-time Fourier transform is deployed to reconstruct the time-frequency (TF) spectrogram of echoes. An L-statistics-based algorithm is applied to separate the non-stationary scatterers from a rigid main body in the TF domain. Furthermore, the CS algorithm is used to reconstruct the cross-range image of the main body after mD separation. Compared with direct CS imaging without mD removal, a better image can be obtained. The results of both simulated and real data processing demonstrate the validity of the proposed method.

Similarities are used with people known already as a means to enhance speaker verification accuracy. Motivated by this, experimental work has been conducted regarding the use of cosine distance (CD) similarity with respect to a set of reference speakers, CD features, with a back-end support vector machine (CDF-SVM) classifier for speaker verification. A state-of-the-art i-vector with CD scoring (i-CDS) is used as the baseline system for the experiments and for the computation of CD similarity. Experimental results on the telephone speech of the core short2-short3 conditions of NIST 2008 speaker recognition evaluation (SRE), for female, male and both-gender trials, show that the proposed CDF-SVM outperforms the baseline i-CDS system. The CDF-SVM achieved an absolute improvement of 1.16% in equal error rate (EER) and 0.38% in minimum DCF over the baseline i-CDS for female trials. Similar performance improvements were also obtained for the male and all-gender trials of the SRE. Finally, fusing the CDF-SVM with i-CDS gave the best overall performance, an absolute improvement of 4.19% in EER and 1.99% in minimum DCF, over the individual CDF-SVM system performance for the all-gender trials. Similar performance improvements were also achieved for male and female trials.

In state-of-the-art text-to-speech (TTS) systems the state durations for each phoneme are generated so as to maximise the state sequence probability given the constraint that the sum of all state durations should be equal to the phoneme duration. Such maximisation sometimes results in negative state durations when the specified phoneme duration is less than the sum of the means of all the states of the phoneme. Such discrepancy implicitly results in the violation of the equality constraint. This has implications for speech research problems, in which each phoneme duration is specified. One such problem is the use of the TTS synthesis system for singing voice synthesis research. An algorithm for state duration assignment is derived so as to maximise the probability of the state sequence with the constraints that the sum of state durations should be equal to the total duration of the phoneme and all the state durations must be greater than or equal to 1. Experimental results show that the proposed algorithm always produces state durations greater than or equal to 1 while satisfying the equality constraint.

A baseband digital predistortion (DPD) technique based on a feed-forward neural network (FFNN) is presented. The process of memory polynomial (MP) DPD is time consuming because of the large number of mathematical calculations. The FFNN is adopted to realise the mathematical calculations in MP DPD with direct learning architecture (DLA). The training samples of the FFNN are derived from MP DPD with DLA. It guarantees the accuracy of imitating the MP DPD. Although the training of the FFNN is time consuming, the trained FFNN DPD is less time consuming than MP DPD. This solution is validated based on a power amplifier (PA) ZFL-2500 driven by a wideband code division multiple access (WCDMA) signal with 3.84 MHz bandwidth. The experimental results show that the FFNN can mimic the behaviour of the MP DPD. The proposed DPD achieves a significant improvement in linearity and is stable.

To achieve a good trade-off between accuracy and cost in practical localisation, methods are studied to enhance the accuracy of a low-cost spatially distributed passive localisation system. First, error sources are systematically analysed. Moreover, measurement error mitigation and localisation algorithm optimisation are implemented. Experiments show these methods can enhance the accuracy of the localisation system significantly.

The guard region for a randomly select user is introduced based on the stochastic geometry model. The guard region, through which a frequency reuse criterion is proposed, is calculated based on parameters such as user position, path loss exponents and transmission power. A dynamic frequency reuse scheme based on the guard regions of macrocell users is proposed to mitigate inter-layer interference. A frequency reuse criterion, which changes along with user position adaptively and is derived through stochastic geometry theory, is believed to be the first effort that can be found in the literature.

A fundamental problem for wireless networks is how to select relays from all available network nodes to realise the optimal multi-hop relaying between a source node and a destination node. Mutual interference among wireless nodes makes this problem challenging. A surprising result of the reported work is that interference-free multi-hop relaying can be achieved in full-duplex decode-and-forward relaying. The broadcast nature of wireless transmissions can be exploited without suffering from mutual interference. Then, an efficient relay selection algorithm is developed that finds the optimal hop count and all the relays to maximise the source-destination multi-hop transmission rate. The complexity of the algorithm is O(N ²) only, where N is the number of available network nodes or network size. Interestingly, this wireless network algorithm is similar to the well-known Dijkstra's algorithm of wired networks. Simulations are conducted to demonstrate its optimality and efficiency.

The growing demand for anti-eavesdropping security has inspired the study of physical-layer security in wireless communications. Relay-assisted secure backscatter communications are considered. The secrecy rate of the system is studied and the condition for a positive secrecy rate is analysed. The optimal relay selection algorithm and a suboptimal selection algorithm with much lower computational complexity are proposed. Simulation results show that the designed selection algorithms significantly outperform random selection in terms of average secrecy rate. The suboptimal selection approximately achieves the same average secrecy rate as the optimal selection.

A substrate coupling analysis flow is presented. The proposed method is fully compatible with the industry analogue/radio-frequency design methodology, seamlessly integrates into the design environment, provides accurate estimation of the coupling effects and can model adequately all the mask design level isolation performance trends. Its accuracy is confirmed by correlating simulation results against on-wafer silicon measurements in a 28 nm CMOS set of ring oscillators with a carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV, whereas the error sigma is 765 μV.

The UK regulator Ofcom is holding an extensive pilot of TV white space (TVWS) technology in the UK. The Centre for Telecommunications Research, (CTR), London, is leading one of the largest trials within this pilot. On the basis of the UK's TVWS framework and using the capabilities of the CTR regarding the pilot, how much white space is available in London and the capacity that can be achieved as an upper bound by aggregating all available white spaces are assessed.