A review of fault models for lsi/vlsi devices
A review of fault models for lsi/vlsi devices
- Author(s): Silvano Gai ; Marco Mezzalama ; Paolo Prinetto
- DOI: 10.1049/sm.1983.0016
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- Author(s): Silvano Gai 1 ; Marco Mezzalama 1 ; Paolo Prinetto 1
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View affiliations
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Affiliations:
1: Dipartimento di Automatica ed Informatica, Politecnico di Torino, Torino, Italy
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Affiliations:
1: Dipartimento di Automatica ed Informatica, Politecnico di Torino, Torino, Italy
- Source:
Volume 2, Issue 2,
April 1983,
p.
44 – 53
DOI: 10.1049/sm.1983.0016 , Print ISSN 0261-3182, Online ISSN 2053-9096
© The Institution of Electrical Engineers
Published
The review paper deals with problems concerning fault modelling for LSI/VLSI devices. Both random and regular logic are considered, and different fault classes are discussed for each, including stuck-at, bridging, functional and time-dependent faults. Specific fault models are then considered for microprocessors, RAMs and PLAs
Inspec keywords: large scale integration; logic testing
Other keywords:
Subjects: Logic design methods
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