This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
A permanent current in addition to the main clocked current is sometimes used to increase the maximum clock rate of a bipolar latch. Although it speeds up the activation of a clocked differential stage, it deteriorates the latch function by the additional current in the inactive phase of each differential stage. Thus, a keep-alive current must be kept small with respect to the main clocked current. In this Letter, a compensation technique is shown avoiding the erroneous output of a keep-alive current. It still speeds up the activation of the main transistor pair, but results in a constant symmetric offset without affecting the differential value of the output voltage. In simulations of flip-flops and clocked comparators, this compensated keep-alive current has a much larger effect on the maximum clock rate than the uncompensated keep-alive current used so far.
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T.E. Collins ,
V. Manan ,
S.I. Long
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Design analysis and circuit enhancements for high-speed bipolar flip-flops.
IEEE J. Solid-State Circuits
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5 ,
1166 -
1174
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2. Rylyakov, A.: ‘A 51 GHz master–slave latch and static frequency divider in 0.18 μm SiGe BiCMOS’. Proc. of the Bipolar/BiCMOS Circuits and Technology Meeting, 2003, pp. 75–77, .
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