This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Present self-tuning regulator architectures based on recursive least-square estimation are computationally expensive and require large amount of resources and time in generating the first control signal due to computational bottlenecks imposed by the calculations involved in estimation stage, different stages of matrix multiplications and the number of intermediate variables at each iteration and precludes its use in applications that have fast required response times and those which run on embedded computing platforms with low-power or low-cost requirements with constraints on resource usage. A salient feature of this study is that a new modular parallel pipelined stochastic approximation-based self-tuning regulator architecture which reduces the time required to generate the first control signal, reduces resource usage and reduces the number of intermediate variables is proposed. Fast matrix multiplication, pipelining and high-speed arithmetic function implementations were used for improving the performance. Results of implementation demonstrate that the proposed architecture has an improvement in control signal generation time by 38% and reduction in resource usage by 41% in terms of multipliers and 44.4% in terms of adders compared with the best existing related work, opening up new possibilities for the application of online embedded self-tuning regulators.
References
-
-
1)
-
2. Clarke, D.W., Gawthrop, P.J.: ‘Self-tuning controller’, Proc. IEE, 1973, 122, (9), pp. 929–934.
-
2)
-
14. Ananthan, T., Vaidyan, M.V.: ‘A reconfigurable parallel hardware implementation of the self-tuning regulator’, ACM Trans. Reconfigurable Technol. Syst., 2011, 6, (4), pp. 17–21.
-
3)
-
19. Kwatny, H.G., Shen, D.W.C.: ‘Identification of nonlinear systems using a method of stochastic approximation’. Proc. of Joint Automatic Control Conf., 1967, pp. 814–826.
-
4)
-
11. Gopi, S., Vaidyan, V.M., Vaidyan, M.V.: ‘Implementation of FPGA based model predictive control for MIMO systems’. IEEE Conf. on Systems, Process & Control, 2013, pp. 21–24.
-
5)
-
4. Dessaint, L.A., Hebert, B.J., Hoang, L.H., et al: ‘A DSP-based adaptive controller for a smoothing positioning system’, IEEE Trans. Ind. Electron., 1990, 37, (5), pp. 1372–1377 (doi: 10.1109/41.103432).
-
6)
-
8. Chen, X., Akella, V.: ‘Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA’, ACM Trans. Reconfigurable Technol. Syst., 2011, 4, (4), pp. 37:1–37:17 (doi: 10.1145/2068716.2068723).
-
7)
-
6. Han, S.H., Lee, M.H., Mohler, R.R.: ‘Real-time implementation of a robust controller for a robotic manipulator based on digital signal processors’, IEEE Trans. Syst. Man Cybern. A, Syst. Hum., 1999, 29, (2), pp. 194–204 (doi: 10.1109/3468.747854).
-
8)
-
9. Nava, F., Sciuto, D., Santambrogio, M.D., et al: ‘Applying dynamic reconfiguration in the mobile robotics domain: a case study on computer vision algorithms’, ACM Trans. Reconfigurable Technol. Syst., 2011, 4, (3), pp. 29:1–29:22 (doi: 10.1145/2000832.2000841).
-
9)
-
7. Naouar, M.W., Monmasson, E., Naassani, A.A., et al: ‘FPGA-based current controller for AC machine drives’, IEEE Trans. Ind. Electron., 2007, 54, (4), pp. 1907–1925 (doi: 10.1109/TIE.2007.898302).
-
10)
-
20. Lee, C.R., Salcic, Z.: ‘High-performance FPGA-based implementation of Kalman filter’, Microprocess. Microsyst., 1997, 21, (4), pp. 257–265 (doi: 10.1016/S0141-9331(97)00040-9).
-
11)
-
18. Kwatny, H.G.: ‘A note on stochastic approximation algorithms in system identification’, IEEE Trans. Autom. Control, 1972, AC.17, (2), pp. 571–572 (doi: 10.1109/TAC.1972.1100069).
-
12)
-
10. Sreesha, C., Vaidyan, V.M., Vaidyan, M.V.: ‘Novel petrinet and labview based approaches for automation of small scale soap industry with FPGA and comparative evaluation’. IEEE Conf. on Systems, Process & Control, 2013, pp. 25–30.
-
13)
-
15. Salcic, Z., Cao, J., Nguang, S.K.: ‘A floating-point FPGA-based self-tuning regulator’, IEEE Trans. Ind. Electron., 2006, 53, (2), pp. 693–704 (doi: 10.1109/TIE.2006.871702).
-
14)
-
17. Cao, J., Salcic, Z., Nguang, S.K.: ‘A floating-point all hardware self-tuning regulator for second order systems’. Proc. of the IEEE Region 10 Conf. on Computers, Communications, Control and Power Engineering (TENCON), 2002, vol. 3, pp. 1733–1736.
-
15)
-
5. Daniel, H.A., Ruano, A.E.B.: ‘Performance comparison of parallel architectures for real time control’, Microprocess. Microsyst., 1999, 23, (6), pp. 325–336 (doi: 10.1016/S0141-9331(99)00040-X).
-
16)
-
3. Sheirah, M.A., Malik, O.P., Hope, G.S.: ‘Self-tuning microprocessor universal controller’, IEEE Trans. Ind. Electron., 1982, IE-29, (1), pp. 31–38 (doi: 10.1109/TIE.1982.354130).
-
17)
-
16. Cao, J., Salcic, Z., Nguang, S.K.: ‘A generic single-chip second-order system digital self-tuning regulator’. Proc. of the Ninth Mediterranean Conf. Control and Automation, 2001.
-
18)
-
13. Ananthan, T., Vaidyan, M.V.: ‘An FPGA-based parallel architecture for on-line parameter estimation using the RLS identification algorithm’, Microprocess. Microsyst., 2014, 38, (5), pp. 496–508 (doi: 10.1016/j.micpro.2014.03.005).
-
19)
-
12. Ananthan, T., Varghese, M.V., Vaidyan, M.V.: ‘Novel FPGA based controller design platform for DC–DC buck converter using HDL co-simulator and XILINX system generator’. IEEE Symp. on Industrial Electronics and Applications, 2012, pp. 270–274.
-
20)
-
2. Clarke, D.W., Gawthrop, P.J.: ‘Self-tuning controller’, Proc. IEE, 1973, 122, (9), pp. 929–934.
-
21)
-
1. Aström, K.J., Wittenmark, B.: ‘On self-tuning regulators’, Automatica, 1973, 9, (2), pp. 185–199 (doi: 10.1016/0005-1098(73)90073-3).
http://iet.metastore.ingenta.com/content/journals/10.1049/joe.2014.0348
Related content
content/journals/10.1049/joe.2014.0348
pub_keyword,iet_inspecKeyword,pub_concept
6
6