This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs and pipelined TDCs are studied and their pros and cons are compared. Noise-shaping TDCs that reduce in-band noise below technology limit are investigated. These TDCs include gated ring oscillator TDCs, switched ring oscillator TDCs, relaxation oscillator TDCs, ΔΣ TDCs and MASH TDCs. The performance of sampling and noise-shaping TDCs is compared. The direction of future research on TDCs is explored.

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