Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm
- Author(s): Chitrakant Sahu 1 and Jawar Singh 1
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View affiliations
-
Affiliations:
1:
Department of Electronics and Communication Engineering , PDPM Indian Institute of Information Technology , Design and Manufacturing Jabalpur , Madhya Pradesh , India
-
Affiliations:
1:
Department of Electronics and Communication Engineering , PDPM Indian Institute of Information Technology , Design and Manufacturing Jabalpur , Madhya Pradesh , India
- Source:
Volume 2014, Issue 3,
March
2014,
p.
105 – 110
DOI: 10.1049/joe.2013.0269 , Online ISSN 2051-3305
This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Received
06/01/2014,
Accepted
17/02/2014,
Published
20/02/2014
The design and characteristics of double-gate (DG) junctionless (JL) devices are compared with the DG inversion-mode (IM) field effect transistors (FETs) at 45 nm technology node with effective channel length of 18 nm. The comparison are performed at iso-V th for both n- and p-type of devices. The JL device shows lower drain-induced barrier lowering, steep subthreshold slope and lower OFF state current. For the first time, the authors demonstrate a pass gate (PG) logic, inverter circuit and static random access memory (SRAM) stability analysis using JL devices, rather than a complementary metal-oxide semiconductor (CMOS) configuration. They observed that transient response of JL PG configuration is similar to that of conventional CMOS PGs. JL inverter also shows similar transient characteristics with 25% reduction in delay and 12% improvement in 6 T SRAM cell stability compared with IMFETs, which shows large potential in digital circuit applications. The simulations were performed using coupled device-circuit methodology in ATLAS technology aided computer design (TCAD) mixed-mode simulator.
Inspec keywords: technology CAD (electronics); transient response; invertors; semiconductor device models; field effect transistors; CMOS integrated circuits; SRAM chips
Other keywords: inverter circuit; static random access memory; double gate junctionless transistors; lower OFF state current; steep subthreshold slope; DG inversion-mode FETs; SRAM cell stability; coupled device-circuit methodology; ATLAS TCAD mixed-mode simulator; CMOS configuration; complementary metal-oxide semiconductor configuration; transient response; pass gate logic; drain-induced barrier lowering; field effect transistors
Subjects: Insulated gate field effect transistors; Semiconductor device modelling, equivalent circuits, design and testing; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing; Computer-aided circuit analysis and design; Memory circuits; Power electronics, supply and supervisory circuits
References
-
-
1)
-
7. Chen, Z., Xiao, Y., Tang, M., et al: ‘Surface-potential-based drain current model for long-channel junctionless double-gate mosfets’, IEEE Trans. Electron Devices, 2012, 59, (12), 3292–3298 (doi: 10.1109/TED.2012.2221164).
-
-
2)
-
17. Gundapaneni, S., Ganguly, S., Kottantharayil, A., et al: ‘Bulk planer junctionless tran-sistor (BPJLT): An attractive device alternative for scaling’, IEEE Elec. Dev. Lett., 2011, 32, (3), pp. 261–263 (doi: 10.1109/LED.2010.2099204).
-
-
3)
-
3. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., Elewa, T.: ‘Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly performance’, IEEE Electron Device Lett., 1987, EDL-8, (9), pp. 410–412 (doi: 10.1109/EDL.1987.26677).
-
-
4)
-
20. Grasser, T., Selberherr, S.: ‘Mixed-mode device simulation’, Microelectron. J., 2000, 31, (11-12), pp. 873–881 (doi: 10.1016/S0026-2692(00)00083-5).
-
-
5)
-
14. Han, M.-H., Chang, C.-Y., Chen, H.-B., Cheng, Y.-C., Wu, Y.-C.: ‘Device and circuit performance estimation of junctionless bulk finFETs’, IEEE Trans. Electron Devices, 2013, 60, (6), 1807–1813 (doi: 10.1109/TED.2013.2256137).
-
-
6)
-
15. Han, M.-H., Chang, C.-Y., Jhan, Y.-R., et al: ‘Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis’, IEEE Electron Device Lett., 2013, 34, (2), pp. 157–159 (doi: 10.1109/LED.2012.2229105).
-
-
7)
-
16. Su, C.J., Tsai, T.I., Liou, Y.L., Lin, Z.M., Lin, H.C., Chao, T.S.: ‘Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels’, Electron Device Lett., 2011, 32, pp. 521–523 (doi: 10.1109/LED.2011.2107498).
-
-
8)
-
1. Colinge, P.J., Lee, W.C., Afzalian, A., et al: ‘Nanowire transistors without junctions’, Nat. Nanotechnol., 2010, 5, pp. 225–229 (doi: 10.1038/nnano.2010.15).
-
-
9)
-
18. Agrawal, S., Fossum, J.G.: ‘On the suitability of a high-k gate dielectric in nanoscale finFET CMOS technology’, IEEE Trans. Electron Devices, 2008, 55, (7), pp. 1714–1719 (doi: 10.1109/TED.2008.925161).
-
-
10)
-
21. Seevinck, E., List, F.J., Lohstroh, J.: ‘Static-noise margin analysis of MOS SRAM cells’, IEEE J. Solid-State Circuits, 1987, 22, (5), pp. 748–754 (doi: 10.1109/JSSC.1987.1052809).
-
-
11)
-
9. Duarte, J.P., Choi, S.-J., Choi, Y.-K.: ‘A full-range drain current model for double-gate junctionless transistors’, IEEE Trans. Electron Devices, 2011, 32, (6), 704–706 (doi: 10.1109/LED.2011.2127441).
-
-
12)
-
23. Li, Y., Cheng, H.-W., Han, M.-H.: ‘Statistical simulation of static noise margin variability in static random access memory’, IEEE Trans. Semicond. Manuf., 2010, 23, (4), pp. 509–516 (doi: 10.1109/TSM.2010.2056710).
-
-
13)
-
22. Bhavnagarwala, A.J., Tang, X., Meindl, J.D.: ‘The impact of intrinsic device fluctuations on CMOS SRAM cell stability’, IEEE J. Solid-State Circuits, 2001, 36, (4), pp. 658–665 (doi: 10.1109/4.913744).
-
-
14)
-
12. Trevisoli, R., Doria, R., de Souza, M., Das, S., Ferain, I., Pavanello, M.: ‘Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors’, IEEE Trans. Electron Devices, 2012, 59, (12), pp. 3510–3518 (doi: 10.1109/TED.2012.2219055).
-
-
15)
- E. Seevinck , F.J. List , J. Lohstroh . Static-noise margin analysis of MOS SRAM cells. IEEE J. Solid-State Circuits , 748 - 754
-
16)
-
17. International Technology Roadmaps for Semiconductor, ITRS, London, UK, 2008 ed., 2008.
-
-
17)
-
10. Bulk Planar Junctionless Transistor (BPJLT): ‘An attractive device alternative for scaling’, IEEE Electron Device Lett., 2011, 32, (3), 261–263 (doi: 10.1109/LED.2010.2099204).
-
-
18)
- J.P. Colinge , C.W. Lee , A. Afzalian . Nanowire transistors without junctions. Nature Nanotechnol. , 225 - 229
-
19)
-
19. A.U. Manual. Device simulation software. In Silvaco Int., Santa Clara, CA, 2008.
-
-
20)
-
13. Lilienfeld, J.E.: ‘Method and apparatus for controlling electric cur-rent’. U.S. Patent 1 745 175, 1925.
-
-
21)
-
22. Bhavnagarwala, A.J., Tang, X., Meindl, J.D.: ‘The impact of intrinsic device fluctuations on CMOS SRAM cell stability’, IEEE J. Solid-State Circuits, 2001, 36, (4), pp. 658–665 (doi: 10.1109/4.913744).
-
-
22)
-
6. Jeon, D.-Y., Park, S.J., Mouis, M., Barraud, S., Kim, G.-T., Ghibaudo, G.: ‘A new method for the extraction of flat-band voltage and doping concentration in tri-gate Junctionless transistors’, J. Solid-State Electron., 81, (2013), pp. 113–118.
-
-
23)
-
16. Su, C.J., Tsai, T.I., Liou, Y.L., Lin, Z.M., Lin, H.C., Chao, T.S.: ‘Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels’, Electron Device Lett., 2011, 32, pp. 521–523 (doi: 10.1109/LED.2011.2107498).
-
-
24)
-
12. Trevisoli, R., Doria, R., de Souza, M., Das, S., Ferain, I., Pavanello, M.: ‘Surface-potential-based drain current analytical model for triple-gate junctionless nanowire transistors’, IEEE Trans. Electron Devices, 2012, 59, (12), pp. 3510–3518 (doi: 10.1109/TED.2012.2219055).
-
-
25)
-
5. Park, C.-H., Ko, M.-D., Kim, K.-H., et al: ‘Electrical characteristics of 20-nm junctionless Si nanowire transistors’, Solid State Electron., 2012, 73, (7), p. 710.
-
-
26)
-
2. Colinge, J.P., Gao, M.H., Romano, A., Maes, H., Claeys, C.: ‘Silicon-on-insulator gate-all-around device’. IEDM Technical Digest, 1990, pp. 595–598.
-
-
27)
-
15. Han, M.-H., Chang, C.-Y., Jhan, Y.-R., et al: ‘Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis’, IEEE Electron Device Lett., 2013, 34, (2), pp. 157–159 (doi: 10.1109/LED.2012.2229105).
-
-
28)
-
24. Razavi, P., Ferain, I., Das, S., Yu, R., Akhavan, N.D., Colinge, J.: ‘Intrinsic gate delay and energy-delay product in junctionless nanowire transistors’. 2012 13th Int. Conf. Ultimate Integration on Silicon (ULIS), 6–7 March 2012, pp. 125–128.
-
-
29)
-
1. Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Colinge, J.P.: ‘Junctionless multigate field-effect transistor’, Appl. Phys. Lett., 2009, 94, pp. 053511-1–053511-2.
-
-
30)
-
9. Duarte, J.P., Choi, S.-J., Choi, Y.-K.: ‘A full-range drain current model for double-gate junctionless transistors’, IEEE Trans. Electron Devices, 2011, 32, (6), 704–706 (doi: 10.1109/LED.2011.2127441).
-
-
31)
-
7. Chen, Z., Xiao, Y., Tang, M., et al: ‘Surface-potential-based drain current model for long-channel junctionless double-gate mosfets’, IEEE Trans. Electron Devices, 2012, 59, (12), 3292–3298 (doi: 10.1109/TED.2012.2221164).
-
-
32)
-
11. Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Colinge, J.P.: ‘Junctionless multigate field-effect transistor’, Appl. Phys. Lett., 2009, 94, pp. 1053511–1053511-2.
-
-
33)
-
14. Han, M.-H., Chang, C.-Y., Chen, H.-B., Cheng, Y.-C., Wu, Y.-C.: ‘Device and circuit performance estimation of junctionless bulk finFETs’, IEEE Trans. Electron Devices, 2013, 60, (6), 1807–1813 (doi: 10.1109/TED.2013.2256137).
-
-
34)
-
23. Li, Y., Cheng, H.-W., Han, M.-H.: ‘Statistical simulation of static noise margin variability in static random access memory’, IEEE Trans. Semicond. Manuf., 2010, 23, (4), pp. 509–516 (doi: 10.1109/TSM.2010.2056710).
-
-
35)
-
3. Balestra, F., Cristoloveanu, S., Benachir, M., Brini, J., Elewa, T.: ‘Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly performance’, IEEE Electron Device Lett., 1987, EDL-8, (9), pp. 410–412 (doi: 10.1109/EDL.1987.26677).
-
-
36)
-
18. Agrawal, S., Fossum, J.G.: ‘On the suitability of a high-k gate dielectric in nanoscale finFET CMOS technology’, IEEE Trans. Electron Devices, 2008, 55, (7), pp. 1714–1719 (doi: 10.1109/TED.2008.925161).
-
-
37)
-
20. Grasser, T., Selberherr, S.: ‘Mixed-mode device simulation’, Microelectron. J., 2000, 31, (11-12), pp. 873–881 (doi: 10.1016/S0026-2692(00)00083-5).
-
-
1)
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