Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

Lei Sun; Kong-Pang Pun; Wai-Tung Ng

Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

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Author(s): Lei Sun¹ ; Kong-Pang Pun¹ ; Wai-Tung Ng²
- Affiliations: 1: Department of Electronic Engineering , Chinese University of Hong Kong , Shatin , Hong Kong, N.T. , People's Republic of China ;
  2: Department of Electrical & Computer Engineering , University of Toronto , 10 King's College Road , Toronto , Canada
Source: Volume 2014, Issue 1, January 2014, p. 45 – 48
DOI: 10.1049/joe.2013.0219 , Online ISSN 2051-3305

This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)

Received 22/11/2013, Accepted 13/12/2013, Published 03/01/2014

This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs) of successive approximation register analog-to-digital converter (ADC). Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V _cm-based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL)/integral non linearity (INL) performance.

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Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

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