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access icon openaccess Impact of body biasing on the retention time of gain-cell memories

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References

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      • 1. Chun, K.C., Jain, P., Kim, T.H., et al: ‘A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2 T gain cell for high speed on-die caches’. IEEE JSSC, 2012.
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      • 2. Teman, A., Meinerzhagen, P., Burg, A., et al: ‘Review and classification of gain cell eDRAM implementations’. Proc. IEEE IEEEI, 2012.
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      • 3. Meinerzhagen, P., Teman, A., Mordakhay, A., et al: ‘A sub-VT 2 T gain-cell memory for biomedical applications’. Proc. IEEE SubVt, 2012.
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      • 4. Meinerzhagen, P., Teman, A., Giterman, R., et al: ‘Exploration of sub-VT and near-VT 2 T gain-cell memories for ultra-low power applications under technology scaling’. JLPEA, 2013.
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      • 5. Lee, Y., Chen, M.T., Park, J., et al: ‘A 5.4nW/kB retention power logic-compatible embedded DRAM with 2 T dual-Vt gain cell for low power sensing applications’. Proc. IEEE A-SSCC, 2010.
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      • 6. Iqbal, R., Meinerzhagen, P., Burg, A., et al: ‘Two-port low-power gain-cell storage array: voltage scaling and retention time’. Proc. IEEE ISCAS, 2012.
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      • 7. Teman, A., Yadid-Pecht, O., Fish, A., et al: ‘Leakage reduction in advanced image sensors using an improved AB2C scheme’, IEEE Sens. J., 2012.
    8. 8)
      • 8. Chun, K.C., Zhang, W., Jain, P., et al: ‘A 2T1C embedded DRAM macro with no boosted supplies featuring a 7 T SRAM based repair and a cell storage monitor’. IEEE JSSC, 2012.
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