Re-scalable V-BLAST MIMO system for FPGA

M.A. McKeown; I.A.B. Lindsay; D.G.M. Cruickshank; J.S. Thompson; S.A. Farson; Y. Hu

Re-scalable V-BLAST MIMO system for FPGA

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Re-scalable V-BLAST MIMO system for FPGA

Author(s): M.A. McKeown ; I.A.B. Lindsay ; D.G.M. Cruickshank ; J.S. Thompson ; S.A. Farson ; Y. Hu
DOI: 10.1049/ip-vis:20045063

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Author(s): M.A. McKeown ¹ ; I.A.B. Lindsay ² ; D.G.M. Cruickshank ² ; J.S. Thompson ² ; S.A. Farson ³ ; Y. Hu ³
- Affiliations: 1: Institute for System Level Integration, Livingston, UK
  2: School of Engineering and Electronics, The University of Edinburgh, Edinburgh, UK
  3: School of Engineering and Electronics, Amphion Semiconductor Ltd., Belfast, UK
Source: Volume 153, Issue 6, December 2006, p. 747 – 753
DOI: 10.1049/ip-vis:20045063 , Print ISSN 1350-245X, Online ISSN 1359-7108

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The development of a re-scalable hardware implementation of a V-BLAST (Vertical Bell Labs Space–Time) multiple input multiple output system for future wireless communications systems is described. Re-scalability will support rapid prototyping of such systems. A floating-point model of the re-scalable system is constructed to guide the development of a fixed-point model, and subsequently a re-scalable hardware implementation. The system uses the Gauss–Jordan elimination method to perform channel matrix inversion and altering the division-by-zero threshold in this matrix inversion process is shown to have a significant effect on bit error rate performance results. The re-scalable hardware implementation is described in a hardware description language in the form of an intellectual property block and several V-BLAST systems are synthesised onto field programmable gate arrays.

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