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Implementation of 0.18 μm RFCMOS technology for system-on-a-chip applications

Implementation of 0.18 μm RFCMOS technology for system-on-a-chip applications

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The paper presents a complete portfolio of RF and baseband components by adopting RFCMOS technology for single-chip systems. Using optimised CMOS topology and deep n-well, the performance relates to the ft of 60 GHz and fmax of 53 GHz at 10 mA, an ft of 70 GHz and fmax of 58 GHz at maximum-transconductance bias, and a minimum noise figure of 1.5 dB without ground-shielded signal pad. High quality-factor inductors are obtained using thick copper interconnects; the measurement result demonstrates the corresponding quality factor of 18 at 1.7 nH. The MIM capacitors, as well as accumulation-mode MOS and junction varactors are also optimised for improving quality factor. For the purpose of eliminating inter-block coupling noise penetrating through the substrate, a deep n-well isolation and a p-well guard-ring have been adopted to suppress the substrate noise by 25 dB and 10 dB, respectively.

References

    1. 1)
      • J.N. Burghartz , M. Hargrove , C.S. Webster , R.A. Groves , M. Keene , K.A. Jenkins , R. Logan , E. Nowak . RF potential of a 0.18 μm CMOS logic device technology. IEEE Trans. Electron Dev. , 864 - 870
    2. 2)
      • Jagannathan, B., Greenberg, D., Anna, R., Wang, X., Pekarik, J., Breitwisch, M., Erturk, M., Wagner, L., Schnabel, C., Sanderson, D., Csutak, S.: `RF FET layout and modeling for design success in RFCMOS technologies', IEEE Symp. RFIC. Dig., 2005, p. 57–60.
    3. 3)
      • Knopik, V., Belot, D.: `0.18 μm thin oxide CMOS transceiver front-end with integrated Tx/Rx commutator for low cost Bluetooth solutions', IEEE ESSCIRC Dig., 2003, p. 675–678.
    4. 4)
      • Adan, A.O., Fukumi, M., Higashi, K., Suyama, T., Miyamoto, M., Hayashi, M.: `Electromagnetic coupling effects in RFCMOS circuits', IEEE Symp. RFIC. Dig., 2002, p. 293–296.
    5. 5)
      • A.J. Joseph , D.L. Harame , B. Jagannathan , D. Coolbaugh , D. Ahlgren , J. Magerlein , L. Lanzerotti , N. Feilchenfeld , S. Stonge , J. Dunn , E. Nowak . Status and direction of communication technologies—SiGe BiCMOS and RFCMOS. IEEE Proc. , 1539 - 1558
    6. 6)
      • R.P. Jindal . Noise associated with distributed resistance of MOSFET gate structure in integrated circuits. IEEE Trans. Electron Dev.
    7. 7)
      • Joardar, K.: `Signal isolation in BiCMOS mixed mode integrated circuits', IEEE Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1995, p. 178–181.
    8. 8)
      • Rogers, J., Tan, L., Smy, T., Tait, N., Tarr, G.: `A high Q on-chip Cu inductor post process for Si integrated circuits', IEEE IITC, 1999, p. 239–241.
    9. 9)
      • Subbanna, S.: `Prospects of silicon-germanium-based technology for very high-speed circuits', IEEE MTT-S Dig., 2000, p. 361–364.
    10. 10)
      • C.-Y. Lee , T.-S. Chen , C.-H. Kao . Methods for noise isolation in RFCMOS ICs. IEEE Trans. Electron Dev. Lett. , 478 - 480
    11. 11)
      • Komurasaki, H., Heima, T., Miwa, T., Yamamoto, K., Wakada, H., Yasui, I., Ono, M., Sano, T., Sato, H., Miki, T., Kato, N.: `A 1.8-V-operation RFCMOS transceiver for Bluetooth', IEEE Symp. VLSI CKT. Dig., 2002, p. 230–233.
    12. 12)
      • Chatterjee, A., Vasanth, K., Grider, D.T., Nandakumar, M., Pollack, G., Aggarwal, R., Tsai, C.Y., Efland, T., Hellums, J., Rodder, M., Tigelaar, H., Shichijo, H., Morton, A.: `Transistor design issues in integrating analog functions with performance digital CMOS', IEEE Symp. VLSI Tech. Dig., 1999, p. 147–148.
    13. 13)
      • Pekarik, J., Greenberg, D., Jagannathan, B., Groves, R., Jones, J.R., Singh, R., Chinthakindi, A., Wang, X., Breitwisch, M., Coolbaugh, D., Cottrell, P., Florkey, J., Freeman, G., Krishnasamy, R.: `RFCMOS technology from 0.25 μm to 65 nm: the state of the art', IEEE CICC Dig., 2004, p. 217–224.
    14. 14)
      • Y. Cheng , M.J. Deen , C.-H. Chen . MOSFET modeling for RF IC design. IEEE Trans. Electron Dev. , 1286 - 1303
    15. 15)
      • H.S. Bennett . Device and technology evolution for si-based RF integrated circuits. IEEE Trans. Electron Dev. , 1235 - 1258
    16. 16)
      • H.-M. Hsu , J.-G. Su , C.-W. Chen , D.D. Tang , C.H. Chen , J.Y.-C. Sun . Integrated power transistor in 0.18-μm CMOS technology for RF system-on-chip applications. IEEE Trans. Microw. Theory Tech. , 2873 - 2881
    17. 17)
      • Pekarik, J.: `RFCMOS technology from 0.25 μm to 65 nm: the state of the art', IEEE CICC Dig., 2004, p. 217–224.
    18. 18)
      • M. Pfost , H.-M. Rein . Modeling and measurement of substrate coupling in Si-bipolar IC's up to 40 GHz. IEEE J. Solid-State Circuits , 4
    19. 19)
      • P.H. Woerlee , M.J. Knitel , R.V. Langevelde , D.B.M. Klaassen , L.F. Tiemeijer , A.J. Scholten , A.T.A. Duijnhoven . RF-CMOS performance trends. IEEE Trans. Electron Dev. , 1776 - 1782
    20. 20)
      • Groves, R., Malinowski, J., Volant, R., Jadus, D.: `High Q inductors in a SiGe BiCMOS process utilizing a thick metal process add-on module', IEEE Proc. Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 1999, p. 149–152.
    21. 21)
      • Yue, C.P., Wong, S.S.: `Scalability of RF CMOS', IEEE RFIC Dig., 2005, p. 53–56.
    22. 22)
      • Morifuji, E., Momose, H.S., Ohguro, T., Yoshitomi, T., Kimijima, H., Matsuoka, F., Kinugawa, M., Katsumata and, Y., Iwai, H.: `Future perspective and scaling down roadmap for RFCMOS', IEEE Symp. VLSI Tech. Dig., 1999, p. 163–164.
    23. 23)
      • Ono, M., Suematsu, N., Kubo, S., Iyama, Y., Takagi, T., Ishida, O.: `1.9 GHz/5.8 GHz-band on-chip matching Si-MMIC low noise amplifiers fabricated on high resistive Si substrate', IEEE IMS Dig., 1999, p. 493–496.
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