QR-decomposition decision feedback equalisation and finite-precision results

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QR-decomposition decision feedback equalisation and finite-precision results

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The QRD LS algorithm is generally recognised for its superior numerical properties under finite-precision implementation. Furthermore, its systolic architecture is well suited for VLSI implementation. In DFE applications the inherent and implementation nonlinearities make it impossible to analyse precisely all effects of finite-precision arithmetic. The paper presents finite precision results of a QRD LS DFE using the TMS320C25 16-bit precision DSP processors as a simulation platform. Using the bit error rate as a performance measure, results are presented for 2-PSK, 4-PSK and Pi/4-DQPSK modulation formats. Also presented are the numerical accuracy and convergence sensitivity for the filter weights. These results may serve as a basis for practical implementation of QRD LS DFEs.

Inspec keywords: digital signal processing chips; systolic arrays; feedback; least squares approximations; VLSI; phase shift keying; digital arithmetic; digital filters; equalisers

Other keywords: 4-PSK; filter weights; QRD LS algorithm; TMS320C25; simulation platform; DSP processors; decision feedback equalisation; performance measure; 16 bit; VLSI; DFE; bit error rate; 2-PSK; finite-precision arithmetic; Pi/4-DQPSK modulation; convergence sensitivity; systolic architecture; numerical accuracy; QR decomposition

Subjects: Microprocessors and microcomputers; Interpolation and function approximation (numerical analysis); Interpolation and function approximation (numerical analysis); Modulation and coding methods; Digital filters; Digital arithmetic methods; Digital signal processing chips

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