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Modular design space exploration framework for embedded systems

Modular design space exploration framework for embedded systems

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Design space exploration is introduced as one of the major tasks in embedded system design. After reviewing existing exploration methods at various layers of abstraction, a generic approach is described based on multi-objective decision making, black-box optimisation and randomised search strategies. The interface between problem-specific and generic parts of the exploration framework is made explicit by defining an interface called PISA. This specification and implementation interface, and the availability of a wide range of randomised multi-objective search methods, makes the proposed framework accessible to a wide range of exploration problems. It resolves the problem that existing optimisation methods cannot be coupled easily to the problem-specific part of a design exploration tool.

Inspec keywords: search problems; systems analysis; decision making; application program interfaces; optimisation; embedded systems

Other keywords: randomised multi-objective search methods; implementation interface; multi-objective decision making; black-box optimisation; PISA; platform and programming language independent interface for search algorithms; randomised search strategies; modular design space exploration framework; embedded system design; specification interface

Subjects: Systems analysis and programming; General utility programs; Combinatorial mathematics; Optimisation techniques

References

    1. 1)
      • K. Lahiri , A. Raghunathan , S. Dey . Design space exploration for optimizing on-chip communication architectures. IEEE Trans. Comput. Aided Desi. Integr. Circuits Syst. , 952 - 961
    2. 2)
      • Palesi, M., Givargis, T.: `Multi-objective design space exploration using genetic algorithms', Proc. 10th Int. Symp. on Hardware/ Software Codesign, 2002, Estes Park, CO, USA, ACM Press, p. 67–72, 2002.
    3. 3)
      • Knowles, J.D.: `Local-search and hybrid evolutionary algorithms for Pareto optimization', 2002, PhD thesis, University of Reading, UK.
    4. 4)
      • Hekstra, G., Hei, G.L., Bingley, P., Sijstermans, F.: `TriMedia CPU64 design space exploration', Proc. IEEE Int. Conf. on Computer Design, October 1999, p. 593–598.
    5. 5)
      • Bleuler, S., Laumanns, M., Thiele, L., Zitzler, E.: `PISA — a platform and programming language independent interface for search algorithms.', Evolutionary Multi-Criterion Optimization (EMO, 2003), 2003, Milan, Italy, p. 494–508Lect. Notes Comput. Sci., 2003, .
    6. 6)
      • T. Blickle , J. Teich , L. Thiele . System-level synthesis using evolutionary algorithms. J. Des. Autom. Embedded Syst. , 23 - 58
    7. 7)
      • Bambha, N.K., Bhattacharyya, S., Teich, J., Zitzler, E.: `Hybrid search strategies for dynamic voltage scaling in embedded multiprocessors', Proc. Int. 9th Symp. on Hardware/Software Codesign, April 2001, Copenhangen, Denmark, p. 243–248.
    8. 8)
      • Neam, S., Sztipanovits, J., Karsai, G.: `Design-space construction and exploration in platform-based design', ISIS-02-301, Tech., 2002.
    9. 9)
      • L. Thiele , S. Chakraborty , M. Gries , S. Künzli . (2003) Design space exploration of network processor architectures, Network processor design: issues and practices.
    10. 10)
      • Agosta, G., Palermo, G., Silvano, C.: `Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems', Proc. ACM Symp. on Applied Computing, 2004, ACM Press, p. 891–896, 2004.
    11. 11)
      • Bleuler, S., Laumanns, M., Thiele, L., Zitzler, E.: `PISA - A platform and programming language independent interface for search algorithms', Evolutionary Multi-Criterion Optimization (EMO 2003), Apr. 2003, Faro, Portugal, p. 494–508, Lect. Notes Comput. Sci., 2632.
    12. 12)
    13. 13)
      • Zhuge, Q., Shao, Z., Xiao, B., Sha, E.H.-M.: `Design space minimization with timing and code size optimization for embedded DSP', Proc. 1st IEEE/ACM/IFIP Int. Conf. on Hardware/Software Codesign and System Synthesis, 2003, 2003, Newport Beach, CA, USA, ACM Press, p. 144–149, 2003.
    14. 14)
      • S. Rajagopal , J. Cavallaro , S. Rixner . Design space exploration for real-time embedded stream processors. IEEE Micro
    15. 15)
      • K.M. Miettinen . (1999) Nonlinear multiobjective optimization.
    16. 16)
      • Palermo, G., Silvano, C., Zaccaria, V.: `A flexible framework for fast multi-objective design space exploration of embedded systems', PATMOS 2003- Int. Workshop on Power and Timing Modeling, 2003, Torino, Italy, p. 249–258, Lect. Notes Comput. Sci., 2799.
    17. 17)
      • , : Evolutionary Multi-Criterion Optimization (EMO 2001), 2001, Hannover, Germany, Lect. Notes Comput. Sci., 1993.
    18. 18)
      • Abraham, S., Rau, B.R., Schreiber, R.: `Fast design space exploration through validity and quality filtering of subsystem designs', HPL-2000-98, Tech., 1998.
    19. 19)
      • M. Eisenring , L. Thiele , E. Zitzler . Handling conflicting criteria in embedded system design. IEEE Des. Test Comput. , 51 - 59
    20. 20)
      • Zitzler, E., Laumanns, M., Thiele, L.: `SPEA2: Improving the strength Pareto evolutionary algorithm for multiobjective optimization', Evolutionary methods for design, optimization and control with application to industrial problems (EUROGEN 2001), 2001, Athens, Greece, CIMNE, p. 95–100, 2002.
    21. 21)
      • Shivakumar, P., Jouppi, N.P.: `Cacti 3.0:an integrated cache timing, power and area model', 2001/2, Tech. Rep. WRL Research, August 2001.
    22. 22)
    23. 23)
    24. 24)
      • Zitzler, E., Künzli, S.: `Indicator-based selection in multiobjective search', Proc. 8th Int. Conf. on Parallel Problem Solving from Nature (PPSN VIII), September 2004, Birmingham, UK.
    25. 25)
    26. 26)
    27. 27)
      • P. Czyzak , A. Jaszkiewicz . Pareto-simulated annealing – a metaheuristic technique for multi-objective combinatorial optimization. J. Multi-Criteria Decision Anal. , 34 - 47
    28. 28)
      • Gajski, D.D., Vahid, F., Narayan, S., Gong, J.: `System-level exploration with SpecSyn', Proc. 35th Design Automation Conf., 1998, San Francisco, CA, USA, p. 812–81.
    29. 29)
      • T. Back , D.B. Fogel , Z. Michalewicz . (1997) Handbook of evolutionary computation.
    30. 30)
    31. 31)
      • Bruni, D., Bogliolo, A., Benini, L.: `Statistical design space exploration for application-specific unit synthesis', Proc. 38th Design Automation Conf., 2001, ACM Press, p. 641–646, 2001.
    32. 32)
      • Ghosh, A., Givargis, T.: `Analytical design space exploration of caches for embedded systems', Design, Automation and Test in Europe Conf. and Exhibition (DATE 03), March 2003, IEEE Press, p. 10650.
    33. 33)
      • Szymanek, R., Catthoor, F., Kuchcinski, K.: `Time-energy design space exploration for multi-layer memory architectures', Proc. 7th ACM/IEEE Design, Automation and Test in Europe Conf., 2004, ACM Press, p. 10318.
    34. 34)
      • Shiue, W.-T., Chakrabarti, C.: `Memory exploration for low power, embedded systems', Proc. 36th ACM/IEEE Design Automation Conf., 1999, ACM Press, p. 140–145.
    35. 35)
      • K. Deb . (2001) Multi-objective optimization using evolutionary algorithms.
    36. 36)
    37. 37)
      • Schaffer, J.D.: `Multiple objective optimization with vector evaluated genetic algorithms', Proc. Int. Conf. on Genetic Algorithms and Their Applications, 1985, p. 93–100.
    38. 38)
      • Thiele, L., Chakraborty, S., Gries, M., Künzli, S.: `A framework for evaluating design tradeoffs in packet processing architectures', Proc. 39th Design Automation Conf. (DAC), June 2002, New Orleans, LA, USA, ACM Press, p. 880–885, 2002.
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