http://iet.metastore.ingenta.com
1887

Zero-overhead loop controller that implements multimedia algorithms

Zero-overhead loop controller that implements multimedia algorithms

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings - Computers and Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Multimedia algorithms generally consist of regular repetitive loop constructs. The authors present a novel control unit design for implementing such loop intensive algorithms. The proposed architecture, termed a zero-overhead loop controller (ZOLC) exploits the regularity of computations, which is a common characteristic of multimedia algorithms, in order to efficiently support the corresponding datapaths. The ZOLC controls the operations in datapath modules by activating/deactivating their corresponding controlling FSMs. Algorithmic flow dependencies, which determine the appropriate loop sequencing, are mapped onto a look-up table (LUT). For another algorithm to execute, only the LUT context and the FSM configurations have to be reprogrammed, assuming a generic datapath. Thus, partial reconfiguration possibilities to implement multimedia algorithms on programmable platforms can be exploited. As proof-of-concept, implementations of algorithms of the multimedia domain are investigated to evaluate the performance of the proposed unit, against other methods of control. Also, a full-search motion estimation processor employing the ZOLC is synthesised. It is shown that the ZOLC provides flexibility by supporting various algorithms of the multimedia field with performance improvements of up to 2.1 over conventional control methods.

References

    1. 1)
      • Low power digital CMOS design
    2. 2)
    3. 3)
    4. 4)
    5. 5)
      • Lee, L.H., Moyer, W., Arends, J.: `Instruction fetch energy reduction using loop caches for embedded applications with small tight loops', Proc. Int. Symp. on Low Power Electronics and Design, August 1999, San Diego, CA
    6. 6)
      • Exploiting fixed programs in embedded systems: A loop cache example
    7. 7)
      • Wu, C.T., Hwang, T.T.: `Instruction buffering for nested loops in low power design', Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), 26–29 May 2002, Scottsdale, AZ, USA
    8. 8)
      • Uh, G.-R., Wang, Y., Whalley, D., Jinturkar, S., Burns, C., Cao, V.: `Effective exploitation of a zero overhead loop buffer', Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES), May 1999, Atlanta, CA, USA, p. 10–19
    9. 9)
      • Motorola Inc., DSP56300 24-bit digital signal processor family manual, Revision 3.0, December 2000
    10. 10)
    11. 11)
      • Talla, D.: `Architectural techniques to accelerate multimedia applications on general-purpose processors', 2001, PhD, University of Texas at Austin, Austin, TX, USA
    12. 12)
      • Computer architecture: A quantitative approach
    13. 13)
      • Custom memory management methodology
    14. 14)
      • Kougia, S., Chatzigeorgiou, A., Zervas, N., Nikolaidis, S.: `Analytical exploration of power efficient data-reuse transformations on multimedia', Presented at the Int. Conf. on Acoustics, Speech and Signal Processing, May 2001, UT, USA
    15. 15)
      • Smith, M.D., Holloway, G.: `An introduction to machine SUIF and its portable libraries for analysis and optimization', Technical, 2000
    16. 16)
      • Compilers: Principles, techniques and tools
    17. 17)
      • Sander, G.: `Graph layout through the VCG tool', Sep. 26-34, Technical, 26 Sept. 1995
    18. 18)
      • International Organization of Standardization, Working group on coding of moving pictures and audio, MPEG-4 Video Verification Model Version 18.0, Pisa, January 2001
    19. 19)
      • Algorithms, complexity analysis and VLSI architectures for MPEG-4 motion estimation
    20. 20)
      • Wong, S., Vassiliadis, S., Cotofana, S.: `SAD implementation in FPGA hardware', Proc. 12th Annual Workshop on Circuits, Systems, and Signal Processing (PRORISC), 2001
    21. 21)
      • ARM Ltd., http://www.arm.com
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cdt_20041187
Loading

Related content

content/journals/10.1049/ip-cdt_20041187
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address