Owing to their high degree of flexibility and low design-turnaround time, field-programmable-gate-array (FPGA) based designs are becoming very popular. With the availability of different types of FPGA, the need of a unified approach for logic-block-independent technology mapping is being felt increasingly. The paper presents a new approach to efficient realisation of a given combinational function in terms of a prespecified k-input-single-output logic block. All subfunctions of 1 to k inputs realisable by the logic block are generated and kept in a library. The approach is general in the sense that it is not targeted to any specific FPGA built around a specified set of basic blocks. It uses a node-clustering technique for breaking up the given combinational function into subfunctions with special treatment for the fanout nodes. The scheme utilises a novel signature-based strategy to find a match for a subfunction in the library. One contribution is the elegant signature-generation scheme that can be applied for any library-based search problem. The signature is unique for functions of up to four variables and has an aliasing of around 0.5% for functions with larger number of variables. For comparison with other mapping techniques, the KGPMAP algorithm has been applied to several combinational benchmark circuits using Actel's act1-library. The result has been found to be superior to other well known library-based technology mappers and some Actel-specific mappers.