Parallel design of arithmetic coding

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Parallel design of arithmetic coding

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The paper presents a parallel algorithm design for real-time implementation of arithmetic coding. The implementation comprises a parallel-processing array arranged in a tree structure. Within each cycle, a group of input symbols can be encoded. This increases the arithmetic coding speed substantially. Details of a fixed-precision algorithm design, its implementation and simulation of its performance are reported.

Inspec keywords: digital arithmetic; parallel algorithms; encoding

Other keywords: arithmetic coding; fixed-precision algorithm design; real-time implementation; tree structure; parallel design; parallel-processing array; parallel algorithm design

Subjects: Digital arithmetic methods; Parallel programming and algorithm theory

http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cdt_19941387
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