Automated technique for high-level circuit synthesis from temporal logic specifications

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Automated technique for high-level circuit synthesis from temporal logic specifications

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A general-purpose strategy for the synthesis of digital circuits from high-level behavioural specifications expressed in the temporal-logic language Tempura is described. This strategy has been implemented as a synthesis tool called AST, and the application of AST to part of the specification for an error-encoder circuit is examined.

Inspec keywords: circuit CAD; temporal logic; digital circuits; formal specification; specification languages

Other keywords: temporal-logic language; synthesis tool; high-level circuit synthesis; high-level behavioural specifications; AST; error-encoder circuit; digital circuit synthesis; Tempura; temporal logic specifications; general-purpose strategy

Subjects: Formal logic; Electronic engineering computing

http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cdt_19941005
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