http://iet.metastore.ingenta.com
1887

CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis

CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IEE Proceedings - Circuits, Devices and Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In this work we have proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain. A parallel-pipelined architecture has been adopted for the present design to ensure high throughput for real-time applications with the latency equal to twice of CORDIC length plus three extra cycles. This unified architecture includes a combination of linear CORDIC and circular CORDIC with FIFO and a few multiplexers where the selection of window and its length are user defined. We have synthesised this architecture with 0.18 μm CMOS technology using Synopsys Design Analyser. The total estimated dynamic power was found to be 350 mW with an operating frequency of 125 MHz and total cell area 11 mm2 (approximately).

References

    1. 1)
    2. 2)
    3. 3)
    4. 4)
    5. 5)
      • Time-dependent frequency domain principal components analysis of multichannel non-stationary signals
    6. 6)
    7. 7)
    8. 8)
      • Zhong, K., Zhu, G., He, H.: `A single-chip, ultra high-speed FFT architecture', Proc. ASIC, 2003, 5th Int. Conf., Oct. 2003, 2, p. 752–756
    9. 9)
    10. 10)
      • An efficient FFT algorithm for superscalar and VLIW processor architectures
    11. 11)
      • Hung, C.-P., Chen, S.-G., Chen, K.-L.: `Design of an efficient variable-length FFT processor', Proc. Int. Symp. Circuits and Systems, ISCAS '04, 23–26 May 2004, 2, p. 833–836
    12. 12)
      • He, S., Torkelson, M.: `Design and implementation of a 1024-point pipeline FFT processor', Proc. IEEE Custom Integrated Circuits Conf., 11–14 May 1998, p. 131–134
    13. 13)
      • Han, W., Arslan, T., Erdogan, A.T., Hasan, M.: `Multiplier-less based parallel-pipelined FFT architectures for wireless communication applications', Proc. Acoustics, Speech and Signal Processing, (ICASSP '05), IEEE Int. Conf., 18–23 March 2005, 5, p. 45–48
    14. 14)
      • The CORDIC trigonometric computing technique
    15. 15)
      • Walther, J.S.: `A unified algorithm for elementary functions', Proc. Spring Joint Computer Conf., 1971, p. 379–385
    16. 16)
      • A CORDIC arithmetic processorchip
    17. 17)
      • Digital signal processing in VLSI
    18. 18)
      • VLSI digital signal processing systems
    19. 19)
    20. 20)
    21. 21)
    22. 22)
      • A way to build efficient carry skip adders
    23. 23)
      • High speed VLSI multiplication algorithm with a redundant binary addition tree
    24. 24)
      • Low latency time CORDIC algorithms
    25. 25)
    26. 26)
    27. 27)
http://iet.metastore.ingenta.com/content/journals/10.1049/ip-cds_20050280
Loading

Related content

content/journals/10.1049/ip-cds_20050280
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address