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Efficient architecture and hardware implementation of coherent integration processor for digital video broadcast-based passive bistatic radar

Efficient architecture and hardware implementation of coherent integration processor for digital video broadcast-based passive bistatic radar

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In this study, the problem of efficient implementation of a coherent integration processor in passive bistatic radars (PBRs) in the presence of range migration is addressed. The authors present a coherent integration architecture for PBR, which consists of a frequency-domain pulse compression module to reduce the overall runtime for the computation of the cross-ambiguity function, and an efficient decimated keystone transform module based on the chirp z-transform to compensate the range migration. The proposed architecture is then implemented in a hybrid central processing unit plus graphic processing unit scheme. Real measurement data are used to verify the superior integration performance and reduced computational complexity achieved by the proposed scheme.

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