Efficient architecture and hardware implementation of coherent integration processor for digital video broadcast-based passive bistatic radar

Tao Shan; Shengheng Liu; Yimin D. Zhang; Moeness G. Amin; Ran Tao; Yuan Feng

Efficient architecture and hardware implementation of coherent integration processor for digital video broadcast-based passive bistatic radar

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Author(s): Tao Shan ^{1, 2} ; Shengheng Liu ² ; Yimin D. Zhang ¹ ; Moeness G. Amin ¹ ; Ran Tao ² ; Yuan Feng ²
- Affiliations: 1: Center for Advanced Communications, Villanova University, Villanova, PA 19085, USA ;
  2: School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, People's Republic of China
Source: Volume 10, Issue 1, January 2016, p. 97 – 106
DOI: 10.1049/iet-rsn.2015.0006 , Print ISSN 1751-8784, Online ISSN 1751-8792

Received 25/01/2015, Accepted 21/06/2015, Revised 25/05/2015, Published 01/01/2016

In this study, the problem of efficient implementation of a coherent integration processor in passive bistatic radars (PBRs) in the presence of range migration is addressed. The authors present a coherent integration architecture for PBR, which consists of a frequency-domain pulse compression module to reduce the overall runtime for the computation of the cross-ambiguity function, and an efficient decimated keystone transform module based on the chirp z-transform to compensate the range migration. The proposed architecture is then implemented in a hybrid central processing unit plus graphic processing unit scheme. Real measurement data are used to verify the superior integration performance and reduced computational complexity achieved by the proposed scheme.

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Efficient architecture and hardware implementation of coherent integration processor for digital video broadcast-based passive bistatic radar

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