access icon free Development of fault-tolerant MLI topology

© The Institution of Engineering and Technology
Received 04/10/2017, Accepted 19/02/2018, Revised 14/02/2018, Published 20/02/2018

Multilevel inverters (MLIs) have developed deep roots in various industrial sectors owing to their advantages over conventional two-level inverters. However, the reliability of the semiconductor devices has been one of the major concerns for the proper functioning of MLI. Therefore, a novel fault-tolerant topology is proposed in this study. The proposed topology is capable to tolerate single- and multi-switch faults. It has lesser device count compared with the most recent work in the field. Moreover, it achieves inherent voltage balancing across capacitors. The proposed fault-tolerant topology is simulated in MATLAB/Simulink and validated experimentally.

Inspec keywords: invertors; capacitors; fault tolerance

Other keywords: deep roots; MLIs; novel fault-tolerant topology; industrial sectors; semiconductor devices; lesser device count; two-level inverters; fault-tolerant MLI topology; multilevel inverters; multiswitch faults

Subjects: Reliability; Power convertors and power supplies to apparatus; Control of electric power systems; Power electronics, supply and supervisory circuits

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