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access icon free Effective design and implementation of GSS-PLL under voltage dip and phase interruption

  • Author(s): Hany A. Hamed 1 ; Ahmed F. Abdou 2 ; Ehab Bayoumi 3 ; Elwy E. EL-Kholy 4
    • View affiliations
  • Source: Volume 11, Issue 6, 29 May 2018, p. 1018 – 1028
    DOI:  10.1049/iet-pel.2017.0178 , Print ISSN 1755-4535, Online ISSN 1755-4543
© The Institution of Engineering and Technology
Received 03/03/2017, Accepted 17/12/2017, Revised 14/11/2017, Published 02/01/2018

The robust operation of grid-connected converters under non-ideal grids is a challenging topic. Synchronising of converters requires accurate estimation of the grid vector angle which is traditionally performed by phase locked loops (PLLs). Separating the grid voltage and current sequence components is essential for controlling converters under non-ideal grids. In this study, an efficient method to separate the grid sequence components using cascaded delayed signal cancellation (CDSC) is developed. The proposed method is a reduced version of the conventional delayed signal cancellation separation technique. Implementing CDSC in the stationary frame enables for using a higher bandwidth without degrading its filtering capability which enables for using the GSS as a pre-filter stage for the traditional synchronous reference frame PLL. Therefore, the obtained grid sequence separator PLL (GSS-PLL) accurately estimates the grid vector angle under severe conditions. The performance of GSS method as well as GSS-PLL is compared to the conventional multiple second-order generalised integrator (MSOGI) method under unbalance, phase interruption and harmonically distorted grids. The accuracy of the proposed method is verified through simulation and experimental tests. The low computational effort of GSS scheme compared to the MSOGI is a significant advantage which encourages its implantation for most of the grid-connected converters.

Inspec keywords: power convertors; source separation; power grids; synchronisation; filtering theory; phase locked loops

Other keywords: CDSC; multiple second-order generalised integrator method; voltage dip; synchronous reference frame PLL; phase interruption; phase locked loops; stationary frame; GSS-PLL; grid voltage separation; current sequence components; grid sequence components; harmonically distorted grids; delayed signal cancellation separation technique; MSOGI method; grid vector angle estimation; grid-connected converters; grid sequence separator; filtering capability; pre-filter stage; cascaded delayed signal cancellation; nonideal grids

Subjects: Modulators, demodulators, discriminators and mixers; Filtering methods in signal processing; Power electronics, supply and supervisory circuits; Power convertors and power supplies to apparatus

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