Effective design and implementation of GSS-PLL under voltage dip and phase interruption

Effective design and implementation of GSS-PLL under voltage dip and phase interruption

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The robust operation of grid-connected converters under non-ideal grids is a challenging topic. Synchronising of converters requires accurate estimation of the grid vector angle which is traditionally performed by phase locked loops (PLLs). Separating the grid voltage and current sequence components is essential for controlling converters under non-ideal grids. In this study, an efficient method to separate the grid sequence components using cascaded delayed signal cancellation (CDSC) is developed. The proposed method is a reduced version of the conventional delayed signal cancellation separation technique. Implementing CDSC in the stationary frame enables for using a higher bandwidth without degrading its filtering capability which enables for using the GSS as a pre-filter stage for the traditional synchronous reference frame PLL. Therefore, the obtained grid sequence separator PLL (GSS-PLL) accurately estimates the grid vector angle under severe conditions. The performance of GSS method as well as GSS-PLL is compared to the conventional multiple second-order generalised integrator (MSOGI) method under unbalance, phase interruption and harmonically distorted grids. The accuracy of the proposed method is verified through simulation and experimental tests. The low computational effort of GSS scheme compared to the MSOGI is a significant advantage which encourages its implantation for most of the grid-connected converters.


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