Effect of adding DC-offset estimation integrators in there-phase enhanced phase-locked loop on dynamic performance and alternative scheme

Fengjiang Wu; Lujie Zhang; Jiandong Duan

Effect of adding DC-offset estimation integrators in there-phase enhanced phase-locked loop on dynamic performance and alternative scheme

View Fulltext

Author(s): Fengjiang Wu ¹ ; Lujie Zhang ² ; Jiandong Duan ¹
- Affiliations: 1: Department of electrical engineering, Harbin Institute of Technology, Harbin 150001, People's Republic of China;
  2: Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061, USA
Source: Volume 8, Issue 3, March 2015, p. 391 – 400
DOI: 10.1049/iet-pel.2014.0317 , Print ISSN 1755-4535, Online ISSN 1755-4543

Received 09/05/2014, Accepted 10/10/2014, Revised 05/08/2014, Published 12/12/2014

Three-phase enhanced phase-locked loop (3P-EPLL) can estimate the amplitude, frequency and phase angle of the positive sequence of the three-phase inputs without using a synchronous reference frame. However, the presence of DC offsets in the inputs of the conventional 3P-EPLL introduces a periodic ripple in the estimated information. Thus, DC-offset estimation integrators (DCEIs) to estimate and feedback the DC component as an error signal are introduced in 3P-EPLL to eliminate the disturbance. This study presents a comprehensive study of the transient performance of 3P-EPLL with DCEIs, proving that a worse and longer dynamic period is caused by the coupling of the frequency and amplitude loop resulted from DCEI. Further, a hybrid filtering 3P-EPLL based on delayed-signal cancellation to reject the DC component and sliding Goertzel transform-based filter to eliminate the effect of harmonics and unbalanced inputs is proposed. Thus, a correct estimation is achieved even under unbalanced inputs with both DC and harmonic components. A set of detailed experiments of the former three enhanced phase-locked loops (EPLLs) are presented to display the deficit of the conventional EPLLs and better performance of the proposed scheme.

References

1. 1)
  - 22. Wang, Y.F., Li, Y.W.: ‘Analysis and digital implementation of cascaded delayed-signal-cancellation PLL’, IEEE Trans. Power Electron., 2011, 26, (4), pp. 1067–1080 (doi: 10.1109/TPEL.2010.2091150).
2. 2)
  - F. Blaabjerg , R. Teodorescu , M. Liserre , A.V. Timbus . Overview of control and grid synchronization for distributed power generation systems. IEEE Trans. Ind. Electron. , 5 , 1398 - 1406
3. 3)
  - 5. Luo, A., Xiao, H., Ma, F., et al: ‘Distribution static compensator based on an improved direct power control strategy’, IET Power Electron., 2014, 7, (4), pp. 957–964 (doi: 10.1049/iet-pel.2013.0265).
4. 4)
  - 8. Xia, C., Wang, M., Song, Z., Liu, T.: ‘Robust model predictive current control of three-phase voltage source PWM rectiﬁer with online disturbance observation’, IEEE Trans. Ind. Inf., 2012, (3), pp. 459–471 (doi: 10.1109/TII.2012.2187912).
5. 5)
  - 16. Perez, M.A., Espinoza, J.R., Moran, L.A., et al: ‘A robust phase-locked loop algorithm to synchronize static-power converters with polluted AC systems’, IEEE Trans. Ind. Electron., 2008, 55, (5), pp. 2185–2192 (doi: 10.1109/TIE.2008.918638).
6. 6)
  - 19. Yin, Z., Liu, J., Zhong, Y.: ‘Study and control of three-phase PWM rectiﬁer based on dual single-input single-output model’, IEEE Trans. Ind. Inf., 2013, 9, (2), pp. 1064–1073 (doi: 10.1109/TII.2012.2222423).
7. 7)
  - 31. Karimi-Ghartemani, M., Khajehoddin, S.A., Jain, P.K., Bakhshai, A., Mojiri, M.: ‘Addressing DC component in PLL and notch filter algorithms’, IEEE Trans. Power Electron., 2012, 27, (1), pp. 78–86 (doi: 10.1109/TPEL.2011.2158238).
8. 8)
  - 4. Elrayyah, A., Sozer, Y., Elbuluk, M.: ‘Robust phase locked-loop algorithm for single-phase utility-interactive inverters’, IET Power Electron., 2014, 7, (5), pp. 1064–1072 (doi: 10.1049/iet-pel.2013.0351).
9. 9)
  - 23. Karimi-Ghartemani, M., Ooi, B.T., Bakhshai, A.: ‘Application of enhanced phase-locked loop system to the computation of synchrophasors’, IEEE Trans. Power Deliv., 2011, 26, (1), pp. 22–32 (doi: 10.1109/TPWRD.2010.2064341).
10. 10)
  - 25. Wang, Y.F., Li, Y.W.: ‘Three-phase cascaded delayed signal cancellation PLL for fast selective harmonic detection’, IEEE Trans. Ind. Electron., 2013, 60, (4), pp. 1452–1463 (doi: 10.1109/TIE.2011.2162715).
11. 11)
  - 21. Neves, F.A.S., Cavalcanti, M.C., de Souza, H.E.P., Bradaschia, F., Bueno, E.J., Rizo, M.: ‘A generalized delayed signal cancellation method for detecting fundamental-frequency positive-sequence three-phase signals’, IEEE Trans. Power Deliv., 2010, 25, (3), pp. 1816–1825 (doi: 10.1109/TPWRD.2010.2044196).
12. 12)
  - M.K- Ghartemani , H. Karim , M.R. Iravani . A magnitude/phase locked loop systems based on estimation of frequency and In-phase/quadrature-phase amplitudes. IEEE Trans. Industrial Electron. , 2 , 511 - 517
13. 13)
  - J. Svensson , M. Bongiorno , A. Sannino . Practical implementation of delayed signal cancellation method for phase-sequence separation. IEEE Trans. Power Deliv. , 1 , 18 - 26
14. 14)
  - 17. Golestan, S., Ramezani, M., Guerrero, J.M., et al: ‘Moving average filter based phase-locked loops: performance analysis and design guidelines’, IEEE Trans. Power Electron., 2014, 29, (6), pp. 2750–2764 (doi: 10.1109/TPEL.2013.2273461).
15. 15)
  - 3. Chauhan, S.K., Shah, M.C., Tiwari, R.R., et al: ‘Analysis, design and digital implementation of a shunt active power filter with different schemes of reference current generation’, IET Power Electron., 2014, 7, (3), pp. 627–639 (doi: 10.1049/iet-pel.2013.0113).
16. 16)
  - 23. Wang, Y.F., Li, Y.W.: ‘Grid synchronization PLL based on cascaded delayed signal cancellation’, IEEE Trans. Power Electron., 2011, 26, (7), pp. 1987–1997 (doi: 10.1109/TPEL.2010.2099669).
17. 17)
  - 24. Nascimento, P.S.B., de Souza, H.E.P., Neves, F.A.S., Limongi, L.R.: ‘FPGA Implementation of the generalized delayed signal cancellation – phase locked loop method for detecting harmonic sequence components in three-phase signals’, IEEE Trans. Ind. Electron., 2013, 60, (4), pp. 645–658 (doi: 10.1109/TIE.2012.2206350).
18. 18)
  - 19. Wang, L., Jiang, Q., Hong, L., Zhang, C., Wei, Y.: ‘A novel phase-locked loop based on frequency detector and initial phase angle detector’, IEEE Trans. Power Electron., 2013, 28, (10), pp. 4538–4549 (doi: 10.1109/TPEL.2012.2236848).
19. 19)
  - 14. Karimi-Ghartemani, M., Khajehoddin, S.A., Jain, K.P., Bakhshai, A.: ‘Comparison of two methods for addressing DC component in phase-locked loop systems’. Energy Conversion Congress and Exposition (ECCE), 2011, Phoenix, AZ, 17–22 September 2011, pp. 3053–3058.
20. 20)
  - 1. Nicastri, A., Nagliero, A.: ‘Comparison and evaluation of the PLL techniques for the design of the grid-connected inverter systems’. Proc. IEEE Int. Symp. Ind. Electron., July 2010, pp. 3865–3870.
21. 21)
  - 6. Shanthi, P., Govindarajan, U., Parvathyshankar, D.: ‘Instantaneous power-based current control scheme for VAR compensation in hybrid AC/DC networks for smart grid applications’, IET Power Electron., 2014, 7, (5), pp. 1216–1226 (doi: 10.1049/iet-pel.2013.0253).
22. 22)
  - 9. Geng, H., Sun, J., Xiao, S., Yang, G.: ‘Modeling and implementation of an all digital phase-locked-loop for grid-voltage phase detection’, IEEE Trans. Ind. Inf., 2013, 9, (2), pp. 772–780 (doi: 10.1109/TII.2012.2209666).
23. 23)
  - 18. Park, Y., Sul, S., Kim, W., et al: ‘Phase-locked loop based on an observer for grid synchronization’, IEEE Trans. Ind. Appl., 2014, 50, (2), pp. 1256–1265 (doi: 10.1109/TIA.2013.2279194).
24. 24)
  - 31. Karimi-Ghartemani, M., Khajehoddin, S.A., Jain, P.K., Bakhshai, A.: ‘Derivation and design of in-loop filters in phase-locked loop systems’, IEEE Trans. Instrum. Meas., 2012, 61, (4), pp. 930–940 (doi: 10.1109/TIM.2011.2172999).
25. 25)
  - 12. Karimi-Ghartemani, M.: ‘Linear and pseudolinear enhanced phased-locked loop (EPLL) structures’, IEEE Trans. Ind. Electron., 2014, 61, (3), pp. 1464–1474 (doi: 10.1109/TIE.2013.2261035).

Errata

An Erratum has been published for this content:

Erratum: Effect of adding DC-offset estimation integrators in there-phase enhanced phase-locked loop on dynamic performance and alternative scheme

Login

Not registered yet?

Share

Tools

Login to add to favourites

Key

Effect of adding DC-offset estimation integrators in there-phase enhanced phase-locked loop on dynamic performance and alternative scheme

References

Related content