access icon free Analysis and discussion of false triggering of V ce desaturation protection circuit in a T-type neutral point clamped inverter and its solutions

IGBT in a T-type inverter delivers unusual performance when accommodated with the conventional collector–emitter voltage (V ce) desaturation protection circuit. By analysing the switching behaviours in the corresponding control sequence, this study presents a false triggering failure phenomenon on the protection circuit. The phenomenon is theoretically analysed. It is aggravated at a larger load current and influenced by the capacitive effects in the antiparallel diode. Analysis done by the authors is validated in a three-phase 15 kW T-type inverter prototype. A false triggering of the protection circuit occurs when the current commutes among the insulated gate bipolar transistors (IGBTs) as a result of the IGBT characteristics being influenced. This study also puts forward a logic algorithm to provide guidance on hardware drive circuit or digital signal processor design depending on the analysis.

Inspec keywords: insulated gate bipolar transistors; driver circuits; switching convertors; semiconductor diodes; clamps; digital signal processing chips

Other keywords: hardware drive circuit; switching behaviours analysis; logic algorithm; insulated gate bipolar transistor; capacitive effect; IGBT; false triggering failure phenomenon; power 15 kW; load current; digital signal processor design; three-phase T-type neutral point clamped inverter; antiparallel diode; collector–emitter voltage desaturation protection circuit

Subjects: Power electronics, supply and supervisory circuits; Power convertors and power supplies to apparatus; Digital signal processing chips; Insulated gate field effect transistors; Junction and barrier diodes; Bipolar transistors

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